Patents Examined by Christine Oda
  • Patent number: 6559651
    Abstract: A method includes locating an open in a conductive line of an insulated conductor surrounded by an insulative sheath. In accordance with one embodiment, the insulated conductor is beneath an earthen surface and a locator signal and carrier signal including synchronization are introduced into the conductive line. A ground current is capacitively transmitted from capacitive points along the conductive line across the insulative sheath to a ground reference in response to the locator and carrier signals. A ground locator signal and a ground carrier signal are received in response to the ground current flowing past a pickup positioned in electrical communication with earth at a downstream point proximal to one of the capacitive points. The ground locator signal has a real component and a quadrature component and the ground carrier signal has real and quadrature synchronization.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: May 6, 2003
    Inventor: Robert G. Crick
  • Patent number: 6559673
    Abstract: Multiple devices can be tested simultaneously for power continuity or for other power performance characteristic(s). If any of the devices have short circuit defects, for example, the fuse devices connected between these defective devices and a single power supply restrict the amount of current drawn by the defective devices. This allows power continuity testing to continue for all of the other devices. At the same time, the reduced voltage level of the defective devices, caused by the restriction of current by their corresponding fuse device, can be detected by the voltage measurement device. The reduced voltage levels allow the defective devices to be identified by a test control apparatus and to be excluded from subsequent testing.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: May 6, 2003
    Assignee: Intel Corporation
    Inventor: James E. Neeb
  • Patent number: 6560640
    Abstract: Improved techniques that enable wireless devices to implement bookmarks with improved transmission efficiency, reduced user navigation and/or reduced amounts of memory resources are disclosed. One aspect of the improved techniques pertains to use of a compact request from a wireless device to an intermediate server when requesting a document or file by selection of a bookmark. Another aspect of the improved techniques is the ability of a user to select a bookmark to request the associated document or file with reduced user interaction (e.g., a single button action). Still another aspect of the improved techniques is that memory resources of the wireless devices need not be consumed to store network addresses (e.g., URLs) for the bookmarks.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: May 6, 2003
    Assignee: Openwave Systems, Inc.
    Inventor: Paul A. Smethers
  • Patent number: 6559654
    Abstract: A method and system for determining an inductance value of an inductive element are presented. The method includes energizing the inductive element using an N-pulse AC to DC converter in electrical communication with the inductive element and an AC source. The method further includes determining at each of a plurality of periodic time intervals an inductive element voltage value, an inductive element current value, and an equivalent source phase angle. An Nth harmonic impedance squared value is then determined for the inductive element using the inductive element voltage and current values and the equivalent source phase angles. The inductive element inductance value is then calculated using the Nth harmonic impedance squared value and an AC source frequency value.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: May 6, 2003
    Assignee: General Electric Company
    Inventors: Eddy Ying Yin Ho, Craig William Moyer, Luis Jose Garces Rivera
  • Patent number: 6556032
    Abstract: A cartridge (10) includes a chuck plate (12) for receiving a wafer (74) and a probe plate (14) for establishing electrical contact with the wafer. In use, a mechanical connecting device (90) locks the chuck plate and the probe plate fixed relative to one another to maintain alignment of the wafer and the probe plate. Preferably, electrical contact with the wafer is established using a probe card (50) that is movably mounted to the probe plate by means of a plurality of leaf springs (52.) The mechanical connecting device is preferably a kinematic coupling including a male connector (94) and first and second opposed jaws (122, 124.) Each of the jaws is pivotable from a retracted position in which the male connector can be inserted between the jaws and an engaging position in which the jaws prevent withdrawal of the male connector from between the jaws. The male connector is movable between an extended and a retracted position, and is biased towards the retracted position.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: April 29, 2003
    Assignee: Aehr Test Systems
    Inventors: Frank Otto Uher, John William Andberg, Mark Charles Carbone, Donald Paul Richmond, II
  • Patent number: 6556018
    Abstract: A method of locating a defective bulb or socket in a light strand. The method includes connecting an electric power connector interface plug to exhibit an electro magnetic field thereat for checking its wires for operability of a fuse situated in the interface plug, and traversing an electro magnetic field detector along the non-illuminated bulb/sockets starting with the first non-illuminated bulb/socket closest to the interface and continuing in succession down the light strand until a non-illuminated bulb/socket is located that exhibits an electro magnetic field detection test opposite than that of the previous electro magnetic field detection test. Thereby identifying the non-illuminated bulb and/or socket with an electro magnetic field which is directly adjacent to a non-illuminated bulb and/or bulb socket that has no electro magnetic field as defective. If only this bulb is defective, its replacement will illuminate all bulbs in its circuit.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: April 29, 2003
    Inventor: Virgil Benton
  • Patent number: 6556027
    Abstract: Devices, methods and systems are provided for monitoring of industrial processes. Devices and systems are provided which include a controller module connected to a probe module having a specified metallurgy and a resistor module having a specified resistance value which is capable of identifying the metallurgy of the probe module to the controller module. A resistor device including a resistor having a resistance value which identifies a type of metallurgical material is also provided. The devices and systems provided are inexpensive, portable, easy to set-up and operate by unskilled personnel, may be connected to both desktop and portable computerized devices and can provide real-time monitoring of industrial processes.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: April 29, 2003
    Assignee: Ondeo Nalco Company
    Inventor: Rodney H. Banks
  • Patent number: 6556017
    Abstract: A Method and an arrangement providing detection of deteriorated lamp filaments (3) in a lamp circuit (11) fed by constant current, in particular for a lamp supervision system for airfield lights. A change in a constant current fed through a lamp circuit (11) is initiated, whereby the lamp filament resistance is determined once in conjunction with the change in current and once a time period later. A difference between the resistance determinations constitutes the deterioration of a lamp filament (3) in comparison with a threshold value. Hence, no record of previous resistance determinations have to be stored, and lamps (4) can be replaced when the difference matches the threshold value.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 29, 2003
    Assignee: Safegate International AB
    Inventor: Åke Pettersson
  • Patent number: 6556026
    Abstract: There is provided a fluid dynamic bearing evaluating method capable of quantitatively observing a clearance between a shaft 3 and a housing 2 in an operating state and evaluating a fluid dynamic bearing 1 more in detail. This fluid dynamic bearing evaluating method is to evaluate the fluid dynamic bearing 1 by filling a space between the housing 2 and the shaft 3 with an uncharged lubricant, flowing a current through between the housing 2 and the shaft 3 and measuring an electrical resistance value of the fluid dynamic bearing 1 including the lubricant. According to this evaluating method, the lubricant placed between the housing 2 and the shaft 3 is not electrically charged, and therefore, the measured electrical resistance value has a correlation with the clearance between the housing 2 and the shaft 3, and the clearance can be quantitatively observed by this electrical resistance value.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: April 29, 2003
    Assignee: Koyo Seiko Co., Ltd.
    Inventors: Takeharu Ogimoto, Takeshi Takahashi
  • Patent number: 6556024
    Abstract: A capacitance type load sensor is provided with outer and inner tubes made of plastic and formed into a hollow circular cylinder shape and outer and inner electrodes respectively attached to the inner and outer peripheral faces of the outer and inner tubes. A coil spring is disposed within the interior space of the inner tube, and load-applied hooks of the coil spring are individually coupled to respective end walls of the outer and inner tubes. When a tensile load is applied to the hooks of the coil spring and hence the coil spring is elongated, a relative motion occurs between the outer and inner tubes so that the facing area between the outer and inner electrodes and accordingly the capacitance between these electrodes decrease. The load sensor measures the applied load based on an amount of change in the capacitance between before and after the application of the load.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 29, 2003
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Katsutoshi Sasaki, Ken Obata, Hiroyuki Yamazaki
  • Patent number: 6552553
    Abstract: A bioelectrical impedance measuring apparatus is provided, which includes a measurement board and two pairs of electrodes arranged on the measurement board. A bioelectrical impedance of a subject is detected bringing both foot soles of the subject into contact with the electrodes. Each of the two pairs of electrodes extends approximately radially from the center of the measurement board.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: April 22, 2003
    Assignee: Tanita Corporation
    Inventors: Tamaki Shoji, Fumie Shibata
  • Patent number: 6552536
    Abstract: A reference standard and method for inspecting dual-layered coatings. The reference standard has a first layer adherent to a substrate, the first layer has a predetermined thickness that increases in one direction. Adherent to the first layer is a second layer, the second layer has a predetermined thickness that increases in a direction orthogonal with the first layer. The orientation of the first and second layers of the reference standard provides a spectrum of the possible variations of the dual-layered coating.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: April 22, 2003
    Assignee: General Electric Company
    Inventor: Richard L. Trantow
  • Patent number: 6552551
    Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michio Komoda, Sigeru Kuriyama
  • Patent number: 6552558
    Abstract: The invention relates to a method comprising supplying a test signal to a first pad part of the pad; measuring the occurrence of the test signal through a second pad part of the pad or a part of the printed circuit board connected to the second pad part, which second pad part is separate from the first pad part, and the leg of the connector is fastened both to the first pad part and to the second pad part during the manufacturing process in order to establish a connection between the pad parts through the leg. The invention further relates to a printed circuit board.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: April 22, 2003
    Assignee: Nokia Corporation
    Inventor: Timo Pinola
  • Patent number: 6549023
    Abstract: An apparatus for measuring the focus of a light exposure system for selectively exposing a photosensitive plate to light rays in a process of fabricating a semiconductor device, wherein there is provided a focus measuring part having opaque region, transparent region, and a transparent electrode arranged in the transparent region, a conducting stage supporting the photosensitive plate; and a capacitance detector for measuring the capacitance between the transparent electrode and the conducting stage.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 15, 2003
    Assignee: Samsung Electric Co., Ltd.
    Inventor: Young-Chang Kim
  • Patent number: 6549017
    Abstract: The on-line winding test unit determines a characteristic signature of a monitored winding(s) in a transformer, generator, or the like. A sensor detects incoming pulses, originating elsewhere on the energy delivery system, applied to the winding. A sensor detects output pulses after each input pulse has propagated through the winding. Data corresponding to the input and output pulses are stored. A processor computes the spectral densities of the data records. The logic then computes the characteristic signature, H(f), for the winding such that H(f) equals the average of Gxy divided by the average of Gxx for the valid data. Coherence is used to determine a valid H(f). A comparison of the H(f)'s over elapsed time using an error function indicates winding deformation or displacement.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: April 15, 2003
    Assignee: Georgia Tech Research Corporation
    Inventor: Larry T. Coffeen
  • Patent number: 6549945
    Abstract: A communication system (100) includes at least one digital signal processor (DSP) and a WAN driver (80) operating on a processor that is electrically coupled to a memory. The WAN driver (80) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: April 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: John C. Sinibaldi, Himanshu Parikh, Veerbhadra S. Kulkarni, David A. Frye, Gary L Turbeville
  • Patent number: 6549016
    Abstract: A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 15, 2003
    Assignee: Xilinx, Inc.
    Inventors: Derek R. Curd, Fariba Farahanchi
  • Patent number: 6545485
    Abstract: An ultrasonic RFI source locator implements signal analysis to discriminate ultrasonic shocks emanating from power line equipment sources from ambient and other interference sources, as well as distinguish between specific type interference sources, such as corona and sparking discharge. The locator has a directional or contact ultrasonic sensor for receiving a signal representing the ultrasonic shocks from a targeted source, and includes signal processing circuitry to detect and compare the strengths of portions of the sensed signal that are modulated at whole integer multiples (harmonics) of an electrical power frequency (e.g., at 60 Hz and 120 Hz on a 60 Hz A/C power system, or 50 Hz and 100 Hz on a 50 Hz A/C power system) with each other, with the total signal and with selected non harmonic frequencies. The locator provides an operator indication of the result of this spectral analysis.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: April 8, 2003
    Assignee: Radar Engineers
    Inventor: John D. Sanderson
  • Patent number: 6545478
    Abstract: The electronic ignition device includes an ignition coil with a primary winding terminal and a secondary winding terminal generating a spark, a power element arranged between the primary winding terminal and ground, a protection circuit issuing a disable signal to the control terminal of the power element in preset conditions, and a voltage limiting circuit having inputs connected to the primary winding terminal and to the battery voltage, and an output connected to the control terminal of the power element. The voltage limiting circuit detects a potential difference between its own inputs and supplies to the control terminal an activation signal for the power element, in presence of the deactivation signal and when the potential difference exceeds the supply voltage by a preset value. Thereby, the voltage limiting circuit limits the voltage on the primary winding terminal to a preset value which depends upon the value of the battery voltage.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: April 8, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventor: Antonino Torres