Abstract: Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.

Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

Abstract: Techniques described and suggested herein include systems and methods for storing, indexing, and retrieving original data of data archives on data storage systems using redundancy coding techniques. For example, redundancy codes, such as erasure codes, may be applied to archives (such as those received from a customer of a computing resource service provider) so as allow the storage of original data of the individual archives available on a minimum of volumes, such as those of a data storage system, while retaining availability, durability, and other guarantees imparted by the application of the redundancy code. Sparse indexing techniques may be implemented so as to reduce the footprint of indexes used to locate the original data, once stored. The volumes may be apportioned into failure-decorrelated subsets, and archives stored thereto may be apportioned to such subsets.

Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.

Abstract: Techniques are described for optimizing a parity-check matrix for a low density parity check (LDPC) encoder. In an example, a first parity-check matrix is accessed. Based on a set of rules, an independent set of check nodes and variable nodes is determined. The set of rules specifies that a check node associated with the first parity-check matrix belongs to the independent set when the check node is connected to only one variable node from the independent set. The set of rules further specifies that a variable node associated with the first parity-check matrix belongs to the independent set when the variable node is connected to only one check node from the independent set. A size of the independent set is based on the set of rules. A second parity-check matrix is generated by at least applying a permutation to the first parity-check matrix based on the independent set.

Abstract: Techniques are disclosed relating to implementation of LDPC encoding circuitry on a single integrated circuit (IC). In some embodiments, circuitry on a single IC includes message circuitry configured to receive or generate a message to be encoded, encode circuitry configured to perform low density parity check (LDPC) encoding on the message, noise circuitry configured to apply noise to the encoded message, and decode circuitry configured to perform LDPC decoding of the message. In some embodiments, the disclosed techniques may reduce production costs (e.g., by reducing overall chip area), facilitate LDPC testing, and/or provide multiple different functions relating to message transmission on a single chip.

Abstract: A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.

Abstract: A method includes: selecting, from M polar codes of a same code length and code rate, a polar code corresponding to an actual code rate for a first transmission, and encoding an information bit sequence by using the polar code to obtain encoded bits; and performing rate matching on the encoded bits to generate to-be-sent bits. Different from a traditional HARQ using one polar code, in this embodiment, a polar code corresponding to the actual code rate for the first transmission is selected from the M polar codes during the initial transmission, so that a different polar code can be selected adaptively according to the actual code rate for the first transmission.

Abstract: The invention relates to a invention relates to a method and decoding device for receiving an input bit-stream comprising a sequence of n-bit pattern symbols as well as a unique n-bit comma symbol for synchronization, and for generating therefrom a synchronized output comprising a sequence of m-bit pattern words, with m<n. The comma symbol allows detection of bit-skip in the input bit-stream, so that the output to be synchronized to compensate for the bit-skip. The decoding device and method of decoding are particularly simple and may be applied in devices, e.g. in a beam modulator array comprising a plurality of decoding devices, and/or in a lithography system comprising such a beam modulator array, in which space and computational resources are scarce while still providing a synchronization capability.

Abstract: A device, system and method for decoding. A noisy version of an error correction codeword may be received, for example, over a noisy communication channel or retrieved from a memory device (e.g. a flash memory device). One or more symbol probabilities may be transformed, from an initial domain to a transformed domain, the symbol probabilities being one or more individual symbols of the received error correction codeword were transmitted as one or more symbols in candidate transmitted error correction codewords. In the transformed domain, a plurality of the transformed symbol probabilities may be composed to generate a combined coset probability defining the likelihood that the transmitted error correction codeword is associated with the individual symbols belongs to a particular one of a plurality of candidate cosets. A plurality of the coset probabilities for the plurality of respective cosets may be inverse transformed from the transformed domain to the initial domain.

Abstract: A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.

Abstract: A system, method and device for error detection/estimation in OFDM communications systems is proposed. The disclosed mechanism allows an efficient error prediction in a received data block (e.g. a packet) without using error detection codes that may impair spectral efficiency (due to the overhead) especially when very small size packets are used. In order to do that, it generates a decision variable with the aim to check whether a received block has errors or not, without resorting to the use of error-detection codes.

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

Abstract: A method includes receiving a first media content item at a media device via a first communications interface. The method also includes receiving, while outputting the first media content item from the media device, at least a first portion of a second media content item at the media device via the first communications interface. The method further includes detecting an error associated with a second portion of the second media content item that is different than the first portion of the second media content item. The method also includes sending a request for the second portion of the second media content item via a second communications interface of the media device.

Abstract: In a method for verifying the integrity of first to Nth binaries (N is a natural number greater than or equal to 2), the method may comprise: loading the first to Nth binaries into a main memory in order to execute the binaries; verifying a self hash to verify, by the Kth binary (K=1, . . . , N?1) which has been loaded into the main memory, the integrity thereof by using a hash; and verifying a link hash by setting any one of the first to Kth binaries as a verification binary and setting a (K+1)th binary to be loaded into the main memory as a binary to be verified so that the verification binary verifies the integrity of the binary to be verified by using a hash.

Abstract: A test system may include: a vector storage unit suitable for storing a first test vector corresponding to a first test operation; a test target suitable for performing a test operation corresponding to the test vector stored in a vector storage unit; a comparison unit suitable for comparing a first test result to an expected value to output a first test result value, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation.

Abstract: According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.

Abstract: An error resilience method comprising: using a computer, creating and storing, in computer memory, one or more FEC filter tables for use by the FEC filter for selectively forwarding a FEC packet; selectively forwarding a request for the FEC packet through a FEC filter based on the FEC table and a dynamic packet loss level at a receiver; limiting a re-transmission request for a particular packet through the FEC filter based on a number of re-transmission requests for the particular packet; and selectively skipping a key frame request based on a number of key frame requests received from a plurality receiver devices, wherein the method is performed by one or more special-purpose computing devices.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: A method and apparatus are provided for transmitting an LDPC code in a multimedia system. The method includes generating an LDPC code based on a resulting parity check matrix which is generated by performing a row splitting operation on a base parity check matrix; and transmitting the LDPC code. The row splitting operation includes splitting each row block included in the base parity check matrix into row blocks, a number of the row blocks is determined based on a splitting factor, and the splitting factor is determined based on a number of repair symbols included in a repair symbol block of the base parity check matrix, a number of rows included in the base parity check matrix, and a scaling factor for determining a size of each permutation matrix in the resulting parity check matrix and a size of each zero matrix included in the resulting parity check matrix.