Patents Examined by Christopher A Culbert
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Patent number: 11903267Abstract: An organic light-emitting display apparatus includes a plurality of first emission units, each including a first organic light-emitting device configured to emit light in at least a first direction and through a first display surface, a plurality of second emission units, each including a second organic light-emitting device configured to emit in a second direction opposite to the first direction and through a second display surface. The first emission units and the second emission units are alternately disposed. The apparatus further includes a transmissive area disposed adjacent to but not overlapping with the plurality of first emission units and the plurality of second emission units when viewed from a direction perpendicular to the first display surface, and capable of transmitting external light through the first and second display surfaces in the transmissive area.Type: GrantFiled: August 29, 2016Date of Patent: February 13, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hae-Kwan Seo, Do-Youb Kim, Bon-Seog Gu
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Patent number: 11894328Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.Type: GrantFiled: May 24, 2022Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jung-Hsing Chien
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Patent number: 11876123Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.Type: GrantFiled: March 29, 2021Date of Patent: January 16, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo
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Patent number: 11830877Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.Type: GrantFiled: November 19, 2019Date of Patent: November 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek
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Patent number: 11805672Abstract: Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.Type: GrantFiled: July 1, 2022Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Masanobu Mizusaki, Masakazu Shibasaki
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Patent number: 11804490Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: GrantFiled: November 23, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Patent number: 11791440Abstract: A method of manufacturing a light emitting element includes forming an n-side electrode at a lateral surface of an n-type semiconductor layer so as not to cover a light extraction surface. Using a portion of a silicon substrate left on an n-type semiconductor layer as a mask, an insulating film formed at a lateral surface of a semiconductor layered body is removed, to expose a lateral surface of the n-type semiconductor layer and a lateral surface of a resin layer. An n-side electrode positioned between the lateral surface of the n-type semiconductor layer and the lateral surface of the resin layer and connected to the exposed lateral surface of the n-type semiconductor layer is formed. Thereafter, the portion of the silicon substrate is removed, to expose the n-type semiconductor layer.Type: GrantFiled: June 11, 2020Date of Patent: October 17, 2023Assignee: NICHIA CORPORATIONInventor: Hirofumi Nishiyama
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Patent number: 11765884Abstract: The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a source region and a drain region in a semiconductor substrate, and a bit line over the source region. The semiconductor device also includes a first epitaxial structure over the drain region, and a capacitor contact over the first epitaxial structure. A bottom surface of the capacitor contact is higher than a bottom surface of the bit line.Type: GrantFiled: November 8, 2019Date of Patent: September 19, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11758709Abstract: The present disclosure relates to a method for preparing a semiconductor device. The method includes forming a source region and a drain region in a semiconductor substrate, and forming a bit line over the source region. The method also includes growing a first epitaxial structure over the drain region. A top surface of the first epitaxial structure is higher than a bottom surface of the bit line. The method further includes forming a capacitor contact over the first epitaxial structure.Type: GrantFiled: October 22, 2021Date of Patent: September 12, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11744139Abstract: A phase-transition optical isomer compound is described, a transparent EL display device including the phase-transition optical isomer compound and a method of fabricating the EL display device, where a phase of the phase-transition optical isomer compound is transited by light irradiation and a second electrode of the EL display device is selectively deposited without a masking process.Type: GrantFiled: September 24, 2021Date of Patent: August 29, 2023Assignee: LG Display Co., Ltd.Inventors: Jun-Sik Hwang, Nam Ki, Chang-Woo Chun, Eun-Ji Sim, Soo-Hyuk Choi
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Patent number: 11737253Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.Type: GrantFiled: June 22, 2017Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl, Mark T. Bohr
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Patent number: 11715639Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.Type: GrantFiled: September 12, 2017Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Chun Sie, Po-Yi Tseng, Chien-Hao Chen, Ching-Lun Lai, David Sung, Ming-Feng Hsieh, Yi-Chi Huang
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Patent number: 11694933Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.Type: GrantFiled: December 12, 2018Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ting Chen, Yi-Hsiu Liu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11682583Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.Type: GrantFiled: December 11, 2018Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
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Patent number: 11653582Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.Type: GrantFiled: November 8, 2018Date of Patent: May 16, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Franck Arnaud, David Galpin, Stephane Zoll, Olivier Hinsinger, Laurent Favennec, Jean-Pierre Oddou, Lucile Broussous, Philippe Boivin, Olivier Weber, Philippe Brun, Pierre Morin
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Patent number: 11631753Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: GrantFiled: February 22, 2019Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Patent number: 11626574Abstract: An organic light-emitting display apparatus includes: a substrate; first and second pixel electrodes on the substrate and spaced from each other; an insulating layer between the first and second pixel electrodes, the insulating layer covering ends of the first and second pixel electrodes, and having a step height difference; an auxiliary electrode on the insulating layer; first and second intermediate layers on the first and second pixel electrodes, the first and second intermediate layers being spaced from each other, and including first and second light-emitting layers, respectively; first and second opposite electrodes on the first and second intermediate layers, the first and second opposite electrodes being spaced from each other, and in contact with the auxiliary electrode; and first and second passivation layers on the first and second opposite electrodes, the first and second passivation layers being spaced from each other, and covering the first and second opposite electrodes, respectively.Type: GrantFiled: April 13, 2020Date of Patent: April 11, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jaesik Kim, Jaeik Kim, Yeonhwa Lee, Joongu Lee, Sehoon Jeong
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Patent number: 11626282Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.Type: GrantFiled: November 8, 2019Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eunkyu Lee, Kyung-Eun Byun, Hyunjae Song, Hyeonjin Shin, Changhyun Kim, Keunwook Shin, Changseok Lee, Alum Jung
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Patent number: 11621381Abstract: A micro-LED mounting structure includes a first layer having a conductive pad disposed on a surface thereof, a second layer including a first surface, a second surface opposite the first surface and disposed on the surface of the first layer, and a via-hole extending from the conductive pad of the first layer to the first surface and including a conductive material, and a micro-LED disposed on the first surface of the second layer to be electrically connected with the conductive material included in the via-hole. The via-hole includes a first opening in the first surface of the second layer and in which the conductive material is formed, the conductive material of the first surface provides a conductive area on a portion of the first surface of the second layer, and the conductive area and an area within a specified area of the conductive area define a substantially flat surface.Type: GrantFiled: November 8, 2019Date of Patent: April 4, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Byunghoon Lee, Jamyeong Koo
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Patent number: 11444207Abstract: A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.Type: GrantFiled: December 12, 2018Date of Patent: September 13, 2022Assignee: International Business Machines CorporationInventors: Babar Khan, Ning Li, Arvind Kumar, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana