Abstract: Provided in the present disclosure is a photoelectric device. For the photoelectric device, a modification layer is added on the surface of a first electrode layer on the side away from a base substrate. The presence of the modification layer can prevent the direct contact of the first electrode layer and other film layers, thereby alleviating the problem of corrosion of indium-containing oxide which constitutes the first electrode layer. Furthermore, an indium-ion trapping group contained in the modification layer can fix indium ions released after the corrosion of the indium-containing oxide to the surface of the first electrode layer, thereby preventing the indium ions from moving to the inner part of the photoelectric device, which can then increase the service life of the photoelectric device.

Abstract: A method manufactures exchange gates from a starting structure including a substrate and, disposed on the substrate, a plurality of gate stacks, each gate stack including, a layer of a conductive or semiconductor material and a layer of a hard mask.

Abstract: The present disclosure relates to an organic light emitting diode (OLED) including plural light emitting material layers disposed between two electrodes and an electron blocking layer, wherein an energy level of the electron blocking layer disposed adjacently to an emitting material layer with relatively low level delayed fluorescent material and an energy level of the delayed fluorescent material are controlled, and an organic light emitting device having the diode. The OLED can lower its driving voltage and maximize its luminous efficiency and luminous lifetime.

Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: Provided is a method of producing a semiconductor optical device that makes it possible to improve the optical device properties of the semiconductor optical device including semiconductor layers containing at least In, As, and Sb. The method has a first step of forming an etching stop layer on an InAs growth substrate; a second step of forming a semiconductor laminate; a third step of forming a distribution portion; a fourth step of bonding the semiconductor laminate and the distribution portion to a support substrate with a metal bonding layer therebetween; and a fifth step of removing the InAs growth substrate.

Abstract: A method of manufacturing a light emitting device that includes providing a first electrode, forming a light emitting layer including quantum dots on the first electrode, forming an electron auxiliary layer on the light emitting layer, and forming a second electrode on the electronic auxiliary layer. The forming of the electron auxiliary layer includes forming an electron auxiliary layer including a plurality of metal oxide nanoparticles, and contacting the plurality of metal oxide nanoparticles with a base including a hydroxyl group (OH).

Abstract: A display module and a display terminal are provided. The display module includes a display panel, a support layer, and a buffer layer, wherein the display panel includes a display portion, a terminal bonding portion, and a bent portion. The support layer is disposed between the display portion and the terminal bonding portion, the buffer layer is disposed on the support layer, the buffer layer includes a first portion and a second portion disposed on a side of the first portion, the second portion corresponds to the terminal bonding portion, and rigidity of the second portion is greater than rigidity of the first portion.

Abstract: A method for preparing a quantum dot light-emitting diode, including the following steps: providing a substrate, the substrate is a cathode substrate; or the substrate is an anode substrate provided with a quantum dot light-emitting layer, and the quantum dot light-emitting layer is arranged on the anode surface of the anode substrate; placing the substrate in an inert atmosphere containing a first gas, and printing an electron transport material ink on the substrate surface to prepare an electron transport layer; preparing other film layers on the electron transport layer to prepare a quantum dot light-emitting diode, the quantum dot light-emitting diode at least includes the following structure: an anode and a cathode arranged oppositely, a quantum dot light-emitting layer arranged between the anode and the cathode, and an electron transport layer arranged between the quantum dot light-emitting layer and the cathode.

Abstract: Various methods and structures for fabricating a semiconductor structure with vertical vias interconnecting BEOL metallization layers. A first BEOL metallization layer includes a first metallization contact. A second BEOL metallization layer is disposed on the first BEOL metallization layer. The second BEOL metallization layer includes a second metallization contact. A dielectric layer is vertically interposed between the first and second metallization layers. A first vertical via interconnects, through the dielectric layer, the first and second metallization contacts. In the first vertical via, a phase change material non-volatile memory (PCM) is vertically interposed between an upper electrode and a lower electrode. The lower electrode is electrically connected to the first metallization contact. The upper electrode is electrically connected to the second metallization contact.

Abstract: The present application relates to a self-assembled monolayer suitable for the modification of electrodes comprised in electronic devices as well as to such electronic devices. The present application also relates to a method for depositing such self-assembled monolayer onto an electrode as well as to the manufacturing of the corresponding devices.

Abstract: Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.

Abstract: A method of forming a graphene device includes: providing a glass substrate with a blocking layer disposed thereon to form a stack; providing a first electrode and a second electrode; increasing the temperature of the stack to at least 100° C.; applying an external electric field (VP) to the first electrode such that at least one metal ion of the glass substrate migrates toward the first electrode to create a depletion region in the glass substrate adjacent the second electrode; decreasing the temperature of the stack to room temperature while applying the external electric field to the first electrode; and after reaching room temperature, setting the external electric field to zero to create a frozen voltage region adjacent the second electrode.

Abstract: A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: A semiconductor light emitting device includes a light emitting structure in the form of a rod, including a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, and having a first surface, a second surface opposing the first surface, and a side surface connecting the first and second surfaces; a regrowth semiconductor layer surrounding an entire side surface of the light emitting structure and having a first thickness in a first position along a perimeter of the side surface and a second thickness, different from the first thickness, in a second position along a perimeter of the side surface; a first electrode on the first surface of the light emitting structure and connected to the first conductivity-type semiconductor layer; and a second electrode on the second surface of the light emitting structure and connected to the second conductivity-type semiconductor layer.