Abstract: A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.

Abstract: A three-dimensional (3D) memory device includes a stack structure including a first stack structure and a second stack structure over the first stack structure, and a barrier layer disposed in a first channel hole in the first stack structure.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

Abstract: An epitaxial structure of a semiconductor light-emitting element includes an n-type layer, a V-pit control layer, a light-emitting layer, and a p-type layer stacked from bottom to top. The light-emitting layer includes a plurality of well layers and a plurality of barrier layers stacked alternately. The V-pit control layer includes a first superlattice layer, and a distance between a bottom surface of the V-pit control layer and a bottom surface of the first superlattice layer is less than or equal to 0.15 ?m. The bottom surface of the first superlattice layer and a bottom surface of the light-emitting layer have a distance therebetween ranging from 0.05 ?m to 0.3 ?m, and each of the first superlattice layer and the light-emitting layer is an Indium (In)-containing layer. A semiconductor light-emitting element and a light-emitting device are also provided.

Abstract: A method for efficiently producing circuit patterns (semiconductor devices) that allows for effortless pickup of circuit patterns after dicing. The method includes producing a semiconductor substrate with circuit patterns formed on a first surface; forming a first laminate by bonding a first support through a first adhesive layer to the first surface; forming a second laminate by bonding a second support through a second adhesive layer having a dot pattern to a second surface opposite to the first surface; debonding the first support from the second laminate; and picking up the circuit patterns from the second support.

Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

Abstract: A semiconductor device includes a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein, a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate, first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction, a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction, and first and second auxiliary channel structures penetrating a part of the first mold structure between the separation structure and the first channel structure, and between the separation structure and the second channel structure.

Abstract: A memory device, and a method of manufacturing the memory device, includes first and second vertical structures spaced apart from each other and a connection structure contacting bottoms of the first and second vertical structures. The memory device also includes a first gate layer disposed between the first and second vertical structures and a second gate layer enclosing the first and second vertical structures and the connection structure. The memory device further includes a global line disposed on the first vertical structure and a local line disposed on the second vertical structure.

Abstract: A three-dimensional memory device may include a lower electrode structure including a plurality of lower electrodes which are vertically stacked on a substrate; a plurality of upper electrode structures disposed on the lower electrode structure, and each including a plurality of upper electrodes which are vertically stacked; and a plurality of shunt structures passing through the plurality of upper electrode structures, and each electrically coupling the plurality of upper electrodes included in the upper electrode structure.

Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

Abstract: A semiconductor device may include: first insulating pillars arranged in a first direction; second insulating pillars arranged alternately with the first insulating pillars and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being greater than the second width; first memory cells located between the second insulating pillars and stacked along a first sidewall of each of the first insulating pillars; and second memory cells located between the second insulating pillars and stacked along a second sidewall of each of the first insulating pillars.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

Abstract: A semiconductor device may include a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer, channel structures passing through the gate structure, and an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between the channel structures.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device may include a stack structure including a plurality of conductive layers, a hole formed in the stack structure, a memory layer allowing a first part and a second part of the hole to be spaced apart from each other in the hole, and a first channel layer disposed in the first part of the hole and a second channel layer disposed in the second part of the hole.

Abstract: A memory device, and a method of manufacturing the same, includes a stack structure and main plugs passing through the stack structure, the main plugs being spaced apart from each other in a first direction. The memory device also includes a separation pattern separating the main plugs in a second direction and a slit pattern separating the stack structure into first and second memory blocks, the slit pattern having an ellipse shape.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.