Abstract: The present invention provides a light-emitting diode structure, comprising a substrate, a first semiconductor layer, a second semiconductor layer, a second electrode and at least one current blocking trench. The substrate includes a first electrode. The first semiconductor layer is located on the substrate. The second semiconductor layer is located on the first semiconductor layer, and a light-emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The second electrode is located on the second semiconductor layer. Each current blocking trench is recessed from a light exit surface of the second semiconductor layer toward the substrate. By means of the at least one current blocking trench, the current flowing from the second electrode flows through the light-emitting layer located outside the second electrode to the first electrode in a diffusing manner.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.

Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

Abstract: A thermally conductive semiconductor packaging structure includes a cooling component exposed on one surface and an electrical interconnecting component on the other surface. The cooling component has a thermally conductive die, its back side is provided with thermally conductive members extending away from the back side, and a front side is provided with pads to connect to the electrical interconnecting component. The electrical interconnecting component includes electrically conductive connectors to connect to the thermally conductive die, a rewiring layer, and metal bumps connecting to the rewiring layer. A substrate, electrically connected to the metal bumps and a heat dissipating cover over the substrate and in contact with the thermally conductive members. The package is applicable to a wide range of packages.

Abstract: A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeOx, SiGe, SiP or SiPOx, where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: 3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.

Abstract: A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.

Abstract: A three-dimensional (3D) memory device includes a stack structure including a first stack structure and a second stack structure over the first stack structure, and a barrier layer disposed in a first channel hole in the first stack structure.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

Abstract: An epitaxial structure of a semiconductor light-emitting element includes an n-type layer, a V-pit control layer, a light-emitting layer, and a p-type layer stacked from bottom to top. The light-emitting layer includes a plurality of well layers and a plurality of barrier layers stacked alternately. The V-pit control layer includes a first superlattice layer, and a distance between a bottom surface of the V-pit control layer and a bottom surface of the first superlattice layer is less than or equal to 0.15 ?m. The bottom surface of the first superlattice layer and a bottom surface of the light-emitting layer have a distance therebetween ranging from 0.05 ?m to 0.3 ?m, and each of the first superlattice layer and the light-emitting layer is an Indium (In)-containing layer. A semiconductor light-emitting element and a light-emitting device are also provided.

Abstract: A method for efficiently producing circuit patterns (semiconductor devices) that allows for effortless pickup of circuit patterns after dicing. The method includes producing a semiconductor substrate with circuit patterns formed on a first surface; forming a first laminate by bonding a first support through a first adhesive layer to the first surface; forming a second laminate by bonding a second support through a second adhesive layer having a dot pattern to a second surface opposite to the first surface; debonding the first support from the second laminate; and picking up the circuit patterns from the second support.

Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

Abstract: A semiconductor device includes a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein, a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate, first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction, a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction, and first and second auxiliary channel structures penetrating a part of the first mold structure between the separation structure and the first channel structure, and between the separation structure and the second channel structure.

Abstract: A memory device, and a method of manufacturing the memory device, includes first and second vertical structures spaced apart from each other and a connection structure contacting bottoms of the first and second vertical structures. The memory device also includes a first gate layer disposed between the first and second vertical structures and a second gate layer enclosing the first and second vertical structures and the connection structure. The memory device further includes a global line disposed on the first vertical structure and a local line disposed on the second vertical structure.

Abstract: A three-dimensional memory device may include a lower electrode structure including a plurality of lower electrodes which are vertically stacked on a substrate; a plurality of upper electrode structures disposed on the lower electrode structure, and each including a plurality of upper electrodes which are vertically stacked; and a plurality of shunt structures passing through the plurality of upper electrode structures, and each electrically coupling the plurality of upper electrodes included in the upper electrode structure.

Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.