Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: Methods, apparatuses, and systems related to semiconductor structure with curved surfaces are described. An example apparatus includes a semiconductor structure comprising a patterned material comprising active areas, a first conductive material on a surface of each active area, and a first metal material on a surface of each first conductive material. The patterned material further includes a second and third conductive material, a first nitride material, and a second nitride material separating each active area, first conductive material, and first metal material from each second and third conductive material, and first nitride material. The apparatus includes a curved surface formed on a portion of the first metal material and second nitride material. The apparatus further includes a first layer comprising an oxide material and a second metal material on the patterned material, where the oxide material contacts the curved surface.

Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

Abstract: A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

Abstract: A display apparatus includes a substrate including a display area and a non-display area outside the display area, a pixel circuit layer disposed on the substrate and including at least one transistor, a first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode spaced apart from each other and disposed on the pixel circuit layer, a first conductive bank layer disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode, a second conductive bank layer disposed on the second sub-pixel electrode and including a second opening overlapping the second sub-pixel electrode, and a third conductive bank layer disposed on the third sub-pixel electrode and including a third opening overlapping the third sub-pixel electrode, wherein the first conductive bank layer, the second conductive bank layer, and the third conductive bank layer are spaced apart from each other.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region; a first insulating layer; a first gate electrode having a first semiconductor layer containing an impurity, a first conductive layer containing titanium, a second conductive layer containing nitrogen and either titanium or tungsten, and a third conductive layer containing tungsten; a second insulating layer provided on the third conductive layer and containing oxygen and silicon; a third insulating layer provided on the second insulating layer and containing nitrogen and silicon; a first contact provided on the first region; a second contact provided on the second region; and a third contact provided on the third conductive layer of the first gate electrode and penetrating through the second insulating layer and the third insulating layer.

Abstract: A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A gate structure is formed on a III-V compound semiconductor layer. A gate silicide layer and a source/drain silicide layer are formed by an anneal process. The gate silicide layer is formed on the gate structure, the source/drain silicide layer is formed on the III-V compound semiconductor layer, and a material composition of the gate silicide layer is different from a material composition of the source/drain silicide layer.

Abstract: An organic light-emitting diode display device can include a display area, a non-display area outside the display area, a plurality of sub-pixels in the display area, each sub-pixel having an emission area and a non-emission area, and an overcoat layer including a plurality of micro lenses in the emission area of each sub-pixel. For an outermost sub-pixel among the plurality of sub-pixels, the overcoat layer has a first flat portion where some micro lenses are removed from the emission area.

Abstract: A semiconductor memory device includes: a stack having conductive layers and insulating layers, the conductive layers including a first select gate line connected to a gate of a first select transistor, a word line provided above the first select gate line and connected to a gate of a memory transistor, and a second select gate line provided above the word line and connected to a gate of a second select transistor; a core insulating layer having a top surface lower than a top surface of the second select gate line; a semiconductor layer having a first semiconductor part having channel formation regions of the transistors and a second semiconductor part on the top surface of the core insulating layer; and a memory layer between the semiconductor layer and the stack. The first semiconductor part has an impurity semiconductor region containing an impurity and overlapping with the second select gate line.

Abstract: The present invention provides a light-emitting diode structure, comprising a substrate, a first semiconductor layer, a second semiconductor layer, a second electrode and at least one current blocking trench. The substrate includes a first electrode. The first semiconductor layer is located on the substrate. The second semiconductor layer is located on the first semiconductor layer, and a light-emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The second electrode is located on the second semiconductor layer. Each current blocking trench is recessed from a light exit surface of the second semiconductor layer toward the substrate. By means of the at least one current blocking trench, the current flowing from the second electrode flows through the light-emitting layer located outside the second electrode to the first electrode in a diffusing manner.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.

Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

Abstract: A thermally conductive semiconductor packaging structure includes a cooling component exposed on one surface and an electrical interconnecting component on the other surface. The cooling component has a thermally conductive die, its back side is provided with thermally conductive members extending away from the back side, and a front side is provided with pads to connect to the electrical interconnecting component. The electrical interconnecting component includes electrically conductive connectors to connect to the thermally conductive die, a rewiring layer, and metal bumps connecting to the rewiring layer. A substrate, electrically connected to the metal bumps and a heat dissipating cover over the substrate and in contact with the thermally conductive members. The package is applicable to a wide range of packages.

Abstract: A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeOx, SiGe, SiP or SiPOx, where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: 3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.

Abstract: A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.