Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

Abstract: A processor having an adaptable and self-setting mode of interfacing with a peripheral storage device is provided. The processor comprises a variable-parameter controller which enables the processor to adaptably interface with a peripheral storage device. Upon powering up, the controller first interfaces with the peripheral storage device in accordance with a default mode of operation of the peripheral storage device to extract configuration data from the peripheral storage device. The configuration data relates to at least one alternate mode of operation of the peripheral storage device. The controller then interfaces with the peripheral storage device in accordance with the alternate mode of operation. The processor includes a memory device connected to the variable-parameter controller for storing the configuration data so that it is accessible to the controller.

Abstract: In a display memory 10, a display data storage area designation register 11 designates a display data storage area, and a mask bit width designation register 12 designates a write mask bit width. According to certain data provided by address parameters of a re-writable memory, the display data storage area designation register, and the mask bit width designation register, a mask control signal generator 13 provides a mask control signal for an external address data to a write control unit 14. The mask control signal is generated from a set of comparisons based on the width of the re-writable memory and the mask bit width to determine what data in the memory may be re-written. The write control unit 14 writes only certain bits of external write data into the display memory 10.

Abstract: A method and an apparatus for reducing data copying overhead associated with protected memory operating systems. In an ATM (Asynchronous Transfer Method) network, the present invention's NIC (network interface circuit) demultiplexes the information in the header of the incoming packet and routes the packet directly to its final destination using the present invention's concept of targeted buffer rings. Thus, instead of having the packet be DMA'd to a buffer in a descriptor ring in the kernel, it may be routed directly to the buffer ring of the destination process.

Abstract: An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.

Abstract: Techniques are presented for efficiently transferring computer code from a source computer to a target computer for execution on the target computer. A virtual memory space for the computer code is created on the target computer. The computer code is linked on the source computer such that addressing of the resulting executable version of the computer code corresponds to the allocated virtual memory space on the target computer. The executable computer code is then stored in the memory of the source computer. As the target computer executes the computer code, page faults result because its allocated virtual memory space is empty. The memory pages required to remediate the page faults are obtained from the source computer on an on-demand basis. Execution accordingly proceeds.

Abstract: A method and apparatus are described for enabling a first node, which utilizes a first naming protocol, to obtain an network address of another node from a naming service that does not provide addresses in accordance with the first naming protocol. A network embodying the present invention includes a naming proxy agent. A first node in the network obtains network addresses corresponding to node names according to a first naming protocol, and a second node conducts network naming operations according to a second naming protocol that is incompatible with the first naming protocol. As a result, the first node cannot by itself obtain the address of the second node by means of a node name query under the first naming protocol.However, the naming proxy agent receives a first naming query transmitted by the first node according to the first naming protocol that includes the name of the second node.

Abstract: Transmission of a first message over a local area network is delayed by a delay value. The delay value is calculated based on a backoff value in a backoff counter and a generated random number. Transmission of the first message is deferred when another node on the local area network begins transmission of another message while transmission of the first message is being delayed for the delay value. The backoff value in the backoff counter is incremented when the transmission of the first message is deferred. The backoff value in the backoff counter is incremented when transmission of the first message collides with transmission of another message by another node on the local area network. The backoff value in the backoff counter is decremented when the first message is transmitted without being deferred and without colliding with transmission of another message.

Abstract: A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.