Abstract: According to one embodiment, extraction circuitry of a decoding device calculates a first code length of a first symbol and a second code length of a second symbol. The extraction circuitry determines first context information corresponding to a third symbol, and second context information corresponding to a fourth symbol, and stores the first context information and first boundary location information, and the second context information and second boundary location information. The extraction circuitry acquires third context information and third boundary location information corresponding to a fifth symbol following the third symbol, and fourth context information and fourth boundary location information corresponding to a sixth symbol following the fourth symbol.

Abstract: According to examples, a compressed memory dump apparatus generates one or more compressed dump files from a virtual address space (VAS) of a target process. Memory regions identified from the VAS are grouped into memory buckets so that a memory bucket includes respective memory regions. Parallel threads are spawned to execute parallel dumping operations. The parallel dumping operations include reading the memory regions, compressing the memory buckets to generate compressed chunks, and writing the compressed chunks to the dump files. A compressed memory dump parser module can be used to retrieve the original memory content from the compressed dump files.

Abstract: Methods, systems, and devices for extended storage for zone metadata with user data in a memory system with a cache are described. The described techniques provide for a memory system to write data and a zone descriptor extension (ZDE) for a zone to a cache before flushing the data and the ZDE to a memory array, which may support re-writable ZDE information. The cache may be addressable using a logical-to-physical (L2P) table, and entries of the L2P table that map the ZDE in the cache may be included after entries of the L2P table that map user data in the cache, and the memory system may identify the current ZDE according to the L2P table region. When the zone is closed, the memory system may flush the data to the zone of the memory array and may migrate the last written ZDE information to a fixed location within the zone.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support row-selective self-refresh operation while a host processor is in sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving, from the host device through the channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear probing filter, or a XOR filter. Other aspects and features are also claimed and described.

Abstract: A link state control method and a data storage system are provided. The method includes: establishing a connection between a host system and a memory device; detecting a temperature of the memory device through the connection; and setting a link state adopted by the connection to one of a plurality of candidate link states according to the temperature.

Abstract: Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans the sorted data set to generate a clean data set based on a policy. The system receives a request for a type of digital output based on the data objects received from the data source and loads a portion of the clean data set to a first level cache. The system selects a machine learning model configured for the type of digital output, and loads a primary cache with a subset of fields stored in the first level cache selected based on the machine learning model. The system generates, based on the first level cache being complete, digital output corresponding to the type of digital output from data in the primary cache.

Abstract: A memory system is connectable to a host. A memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks, each of which is a unit of an erase operation. The controller is electrically connected to the non-volatile memory and controls the non-volatile memory. The controller receives first data from the host. The controller generates third data from the first data by randomizing the first data using second data that has a different value each time the data erase operation is executed on a first block among the plurality of blocks. The controller writes the second data to the non-volatile memory and the third data to the first block.

Abstract: A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: According to one aspect, a decoder is provided. The decoder may include a first memory and a message updating circuit. The first memory may be configured to store posterior probability messages. The message updating circuit may be configured to sequentially read a posterior probability message corresponding to each non-zero sub-matrix of a current layer from the first memory in a first reading order according to a position of each non-zero sub-matrix of the current layer. The message updating circuit may be configured to obtain an updated posterior probability message corresponding to each non-zero sub-matrix of the current layer based on the posterior probability message corresponding to each non-zero sub-matrix of the current layer in a current iteration. The message updating circuit may be configured to sequentially write the updated posterior probability message corresponding to each non-zero sub-matrix of the current layer into the first memory in a first writing order.

Abstract: Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.

Abstract: Examples of the present disclosure provide memory systems and operating methods thereof, and computer-readable storage mediums. An example memory system includes a memory device and a memory controller. The memory controller is configured to obtain a temperature parameter at a first time instance and a temperature parameter at a second time instance, a rate of data transmission at the first time instance, and a thermal throttling parameter at the first time instance and determine an upper limit of the rate of data transmission at a third time instance. The second time instance is at least one time instance before the first time instance, and the third time instance is a time instance after the first time instance.

Abstract: A node determines a frequency offset between a physical layer clock and a local oscillator clock, wherein the node uses the physical layer clock as a clock source for a local time counter. The node tunes, based on the frequency offset, a frequency of the local oscillator clock. The node then identifies an issue that is associated with the physical layer clock and thereby causes the local oscillator clock to be the clock source for the local time counter. The node identifies, after causing the local oscillator clock to be the clock source for the local time counter, that the issue that is associated is resolved or that a time interval has elapsed, and thereby causes the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

Abstract: A method for sharing a storage device among multiple processors and an associated electronic device are provided. The method includes: controlling a first processor and a second processor to operate in an access mode and a detection mode, respectively; in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device; in response to a first predetermined condition, controlling the first processor to enter the detection mode from the access mode; in response to a second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission.

Abstract: An information processing apparatus includes a processor configured to: set a grace period for image deletion in response to transferring one or more images from a first storage area to a second storage area different from the first storage area, according to a user's instruction; and give an instruction to delete, from the first storage area, an image corresponding to the transferred image, in response to a lapse of the grace period starting from the transfer.

Abstract: Systems and methods for coalescing writes to facilitate generation of larger compression groups for use during inline compression are provided. According to one embodiment, inline compression performed by a storage system is improved by temporarily staging writes to in-memory data structures (e.g., inline storage efficiency (ISE) index nodes (inodes)) and performing coalescing in a deferred manner to generate larger compression groups for use during performance of inline compression. In one example, all files may be treated in the same manner, for example, by staging writes within a staging area and then processing the staged data by an inline compression workflow. In another example, the staging processing for small and large file may be different. For instance, the data blocks associated with small files may be staged separately from data blocks associated with large files and/or data blocks of multiple small files may be staged within the same ISE inode.

Abstract: After capacity expansion of a storage system, a large-width target chunk group is generated by using a plurality of original small-width source chunk groups in the storage system. In a stripe of the target chunk group, a check stripe unit part points to a check shard, and a data stripe unit part does not directly point to a data shard, but points to a data stripe unit of a source stripe.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to: perform a first primary node election among a plurality of nodes of an information handling system cluster to determine a first primary node, wherein the first election is based on a common election algorithm; determine a cloud intent associated with the plurality of nodes; in response to a determination that the cloud intent is associated with an additional primary node requirement, perform a second primary node election among the plurality of nodes to determine a second primary node different from the first primary node, wherein the second election is based on a vertical election algorithm; and cause the second primary node to act as a primary node of the cluster of information handling systems.

Abstract: An apparatus may include a storage device that may include at least one storage medium and a controller configured to control the at least one storage medium, wherein the controller may be configured to: receive a write command, wherein the write command may indicate a reclaim unit handle; perform, based on the reclaim unit handle, and based on an operation or condition of the storage device, a selection of a reclaim unit of the at least one storage medium; and store, based on the write command, data to the reclaim unit. The storage medium may include a first reclaim group including the first reclaim unit and a second reclaim group including a second reclaim unit of the at least one storage medium, and the selection of the first reclaim unit may include performing a selection of the first reclaim group.

Abstract: A segment height corresponding to a least common multiple (LCM) of at least two different erase block sizes of solid-state storage devices is selected. A determination as to whether the LCM exceeds a segment height threshold is made. In response to determining that the LCM exceeds the segment height threshold, one or more calculations are performed to determine corresponding pinned space values for different segment heights. A particular segment height from the different segment heights is selected based on the corresponding pinned space values.