Abstract: An information processing apparatus includes a processor configured to: set a grace period for image deletion in response to transferring one or more images from a first storage area to a second storage area different from the first storage area, according to a user's instruction; and give an instruction to delete, from the first storage area, an image corresponding to the transferred image, in response to a lapse of the grace period starting from the transfer.

Abstract: Systems and methods for coalescing writes to facilitate generation of larger compression groups for use during inline compression are provided. According to one embodiment, inline compression performed by a storage system is improved by temporarily staging writes to in-memory data structures (e.g., inline storage efficiency (ISE) index nodes (inodes)) and performing coalescing in a deferred manner to generate larger compression groups for use during performance of inline compression. In one example, all files may be treated in the same manner, for example, by staging writes within a staging area and then processing the staged data by an inline compression workflow. In another example, the staging processing for small and large file may be different. For instance, the data blocks associated with small files may be staged separately from data blocks associated with large files and/or data blocks of multiple small files may be staged within the same ISE inode.

Abstract: After capacity expansion of a storage system, a large-width target chunk group is generated by using a plurality of original small-width source chunk groups in the storage system. In a stripe of the target chunk group, a check stripe unit part points to a check shard, and a data stripe unit part does not directly point to a data shard, but points to a data stripe unit of a source stripe.

Abstract: An apparatus may include a storage device that may include at least one storage medium and a controller configured to control the at least one storage medium, wherein the controller may be configured to: receive a write command, wherein the write command may indicate a reclaim unit handle; perform, based on the reclaim unit handle, and based on an operation or condition of the storage device, a selection of a reclaim unit of the at least one storage medium; and store, based on the write command, data to the reclaim unit. The storage medium may include a first reclaim group including the first reclaim unit and a second reclaim group including a second reclaim unit of the at least one storage medium, and the selection of the first reclaim unit may include performing a selection of the first reclaim group.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to: perform a first primary node election among a plurality of nodes of an information handling system cluster to determine a first primary node, wherein the first election is based on a common election algorithm; determine a cloud intent associated with the plurality of nodes; in response to a determination that the cloud intent is associated with an additional primary node requirement, perform a second primary node election among the plurality of nodes to determine a second primary node different from the first primary node, wherein the second election is based on a vertical election algorithm; and cause the second primary node to act as a primary node of the cluster of information handling systems.

Abstract: A segment height corresponding to a least common multiple (LCM) of at least two different erase block sizes of solid-state storage devices is selected. A determination as to whether the LCM exceeds a segment height threshold is made. In response to determining that the LCM exceeds the segment height threshold, one or more calculations are performed to determine corresponding pinned space values for different segment heights. A particular segment height from the different segment heights is selected based on the corresponding pinned space values.

Abstract: A memory device includes first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values less than or equal to a first reference number, on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation.

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

Abstract: A system for data indexing includes memory and at least one computing device in communication with the memory. The computing device can store data objects in the memory. The computing device can assign an importance level to, or determine an applicable policy for, each data object by at least analyzing each data object to determine an importance level for each data object, designate each data objects having a high importance level as a first-tier data object, and designating each data object having a low importance level as a second-tier data object. The computing device can store subject data for the data objects by at least storing a first amount of subject data for each first-tier data object and a second amount of subject data for each second-tier data object, where the second amount of subject data is less than the first amount of subject data.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: A method for managing data related to a vehicle in which autonomous driving control is performed is provided. In the method, it is determined whether artificial intelligence is involved in computer processing for performing the autonomous driving control. In the method, it is also determined whether a predetermined save condition is satisfied. When it is determined that the artificial intelligence is involved in the computer processing and it is determined that the predetermined save condition is satisfied, input and output data of the computer processing within a predetermined save time is saved based on a timing at which it is determined that the predetermined save condition is satisfied in a memory device of the vehicle.

Abstract: Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.

Abstract: A computer-implemented method for managing tracks in a cache is provided. The computer-implemented method includes instantiating cache control blocks to each manage operations for one of the tracks and instantiating a bitmap corresponding to each of the cache control blocks. Each bitmap includes an active bit indicating whether the one of the tracks for which the corresponding cache control block manages operations is active and additional bits indicating additional characteristics of the one of the tracks for which the corresponding cache control block manages operations.

Abstract: A flat hash table includes a plurality of entries, and each entry includes a hash function index and a usage bitmap. A method for block device level compression mapping using the flat hash table includes compressing uncompressed data to compressed data, retrieving an entry of the flat hash table using an uncompressed block address of the uncompressed data, determining a compressed block address of the compressed data by executing at least one hash function and by determining a hash function in the at least one hash function for mapping the uncompressed block address to the compressed block address that corresponds to a space in a block storage device, storing the compressed data to the space that corresponds to the compressed block address, and updating the hash function index of the entry of the flat hash table with an index indicative of the hash function.

Abstract: A method for operating a computational storage device includes receiving, by a storage controller, a first computing namespace setting instruction from a first host device, receiving, by the storage controller, a second computing namespace setting instruction from a second host device, receiving, by the storage controller, a first program from the first host device, receiving, by the storage controller, a second program from the second host device, receiving, by the storage controller, a fused execution command processing, by a first accelerator, the first computation, storing, by the storage controller, a first computation result obtained by processing the first computation in a buffer memory, providing, by the storage controller, data stored in the buffer memory to a second accelerator different from the first accelerator and processing, by the second accelerator, the second computation on the data provided from the buffer memory.

Abstract: A data storage system, an intelligent network interface card, and a compute node are provided, and belong to the field of data storage. The data storage system includes a compute node and a plurality of storage nodes. The compute node stores metadata, and the metadata may indicate an address at which target data is stored in the plurality of storage nodes. According to this application, the compute node may directly read the target data from a corresponding storage node based on the address indicated by the metadata stored in the compute node, does not need to perform cross-node data forwarding by using the plurality of storage nodes, and does not need to perform a plurality of times of metadata searching. This effectively reduces a data reading delay and improves a data reading speed.

Abstract: The present application discloses a memory chip. The memory chip includes a nonvolatile status register and a control circuit. The nonvolatile status register includes a plurality of groups of registers, each group of the registers includes a flag register and at least one data register, the control circuit is connected to the nonvolatile status register, and is configured to control writing times of the nonvolatile status register being greater than erasing times of the nonvolatile status register.

Abstract: A storage system may include a first device including a transmission circuit configured to generate encrypted first information by encrypting first information of a transmission target message, to generate encrypted second information by encrypting second information of the transmission target message, and to transmit the encrypted first information and the encrypted second information, and a second device including a reception circuit configured to decrypt the encrypted first information by receiving the encrypted first information and the encrypted second information from the first device and to store the first information that has been decrypted and the encrypted second information in a memory device.

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.

Abstract: An operating method of a non-volatile memory device, includes detecting first memory cells having the erase state among memory cells connected with a first word line; detecting second memory cells having sixth or seventh program states connected with a second word line adjacent to the first word line; detecting target bit lines including one of the first memory cells and one of the second memory cells; detecting target bits, corresponding to a target bit line and the erase state, in write data which is to be programmed in third memory cells connected with a third word line adjacent to the second word line; generating flip bit position data based on the target bits; flipping the target bits of the write data to generate flipped data; and programming the flipped data and the flip bit position data in the third word line.