Abstract: A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: According to one aspect, a decoder is provided. The decoder may include a first memory and a message updating circuit. The first memory may be configured to store posterior probability messages. The message updating circuit may be configured to sequentially read a posterior probability message corresponding to each non-zero sub-matrix of a current layer from the first memory in a first reading order according to a position of each non-zero sub-matrix of the current layer. The message updating circuit may be configured to obtain an updated posterior probability message corresponding to each non-zero sub-matrix of the current layer based on the posterior probability message corresponding to each non-zero sub-matrix of the current layer in a current iteration. The message updating circuit may be configured to sequentially write the updated posterior probability message corresponding to each non-zero sub-matrix of the current layer into the first memory in a first writing order.

Abstract: Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.

Abstract: Examples of the present disclosure provide memory systems and operating methods thereof, and computer-readable storage mediums. An example memory system includes a memory device and a memory controller. The memory controller is configured to obtain a temperature parameter at a first time instance and a temperature parameter at a second time instance, a rate of data transmission at the first time instance, and a thermal throttling parameter at the first time instance and determine an upper limit of the rate of data transmission at a third time instance. The second time instance is at least one time instance before the first time instance, and the third time instance is a time instance after the first time instance.

Abstract: A node determines a frequency offset between a physical layer clock and a local oscillator clock, wherein the node uses the physical layer clock as a clock source for a local time counter. The node tunes, based on the frequency offset, a frequency of the local oscillator clock. The node then identifies an issue that is associated with the physical layer clock and thereby causes the local oscillator clock to be the clock source for the local time counter. The node identifies, after causing the local oscillator clock to be the clock source for the local time counter, that the issue that is associated is resolved or that a time interval has elapsed, and thereby causes the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

Abstract: A method for sharing a storage device among multiple processors and an associated electronic device are provided. The method includes: controlling a first processor and a second processor to operate in an access mode and a detection mode, respectively; in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device; in response to a first predetermined condition, controlling the first processor to enter the detection mode from the access mode; in response to a second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission.

Abstract: An information processing apparatus includes a processor configured to: set a grace period for image deletion in response to transferring one or more images from a first storage area to a second storage area different from the first storage area, according to a user's instruction; and give an instruction to delete, from the first storage area, an image corresponding to the transferred image, in response to a lapse of the grace period starting from the transfer.

Abstract: Systems and methods for coalescing writes to facilitate generation of larger compression groups for use during inline compression are provided. According to one embodiment, inline compression performed by a storage system is improved by temporarily staging writes to in-memory data structures (e.g., inline storage efficiency (ISE) index nodes (inodes)) and performing coalescing in a deferred manner to generate larger compression groups for use during performance of inline compression. In one example, all files may be treated in the same manner, for example, by staging writes within a staging area and then processing the staged data by an inline compression workflow. In another example, the staging processing for small and large file may be different. For instance, the data blocks associated with small files may be staged separately from data blocks associated with large files and/or data blocks of multiple small files may be staged within the same ISE inode.

Abstract: After capacity expansion of a storage system, a large-width target chunk group is generated by using a plurality of original small-width source chunk groups in the storage system. In a stripe of the target chunk group, a check stripe unit part points to a check shard, and a data stripe unit part does not directly point to a data shard, but points to a data stripe unit of a source stripe.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to: perform a first primary node election among a plurality of nodes of an information handling system cluster to determine a first primary node, wherein the first election is based on a common election algorithm; determine a cloud intent associated with the plurality of nodes; in response to a determination that the cloud intent is associated with an additional primary node requirement, perform a second primary node election among the plurality of nodes to determine a second primary node different from the first primary node, wherein the second election is based on a vertical election algorithm; and cause the second primary node to act as a primary node of the cluster of information handling systems.

Abstract: An apparatus may include a storage device that may include at least one storage medium and a controller configured to control the at least one storage medium, wherein the controller may be configured to: receive a write command, wherein the write command may indicate a reclaim unit handle; perform, based on the reclaim unit handle, and based on an operation or condition of the storage device, a selection of a reclaim unit of the at least one storage medium; and store, based on the write command, data to the reclaim unit. The storage medium may include a first reclaim group including the first reclaim unit and a second reclaim group including a second reclaim unit of the at least one storage medium, and the selection of the first reclaim unit may include performing a selection of the first reclaim group.

Abstract: A segment height corresponding to a least common multiple (LCM) of at least two different erase block sizes of solid-state storage devices is selected. A determination as to whether the LCM exceeds a segment height threshold is made. In response to determining that the LCM exceeds the segment height threshold, one or more calculations are performed to determine corresponding pinned space values for different segment heights. A particular segment height from the different segment heights is selected based on the corresponding pinned space values.

Abstract: A memory device includes first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values less than or equal to a first reference number, on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation.

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

Abstract: A system for data indexing includes memory and at least one computing device in communication with the memory. The computing device can store data objects in the memory. The computing device can assign an importance level to, or determine an applicable policy for, each data object by at least analyzing each data object to determine an importance level for each data object, designate each data objects having a high importance level as a first-tier data object, and designating each data object having a low importance level as a second-tier data object. The computing device can store subject data for the data objects by at least storing a first amount of subject data for each first-tier data object and a second amount of subject data for each second-tier data object, where the second amount of subject data is less than the first amount of subject data.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: A method for managing data related to a vehicle in which autonomous driving control is performed is provided. In the method, it is determined whether artificial intelligence is involved in computer processing for performing the autonomous driving control. In the method, it is also determined whether a predetermined save condition is satisfied. When it is determined that the artificial intelligence is involved in the computer processing and it is determined that the predetermined save condition is satisfied, input and output data of the computer processing within a predetermined save time is saved based on a timing at which it is determined that the predetermined save condition is satisfied in a memory device of the vehicle.

Abstract: Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.

Abstract: A computer-implemented method for managing tracks in a cache is provided. The computer-implemented method includes instantiating cache control blocks to each manage operations for one of the tracks and instantiating a bitmap corresponding to each of the cache control blocks. Each bitmap includes an active bit indicating whether the one of the tracks for which the corresponding cache control block manages operations is active and additional bits indicating additional characteristics of the one of the tracks for which the corresponding cache control block manages operations.