Abstract: An adaptive, user-centric system and network for controlling power consumption by an appliance is described. The appliance may be any type of powered apparatus, such as A/C units, heaters, computers, lights, kitchen appliances, home media centers, and so on. The power to these appliances is based on an estimated arrival time of the user to the destination where the appliance is located. It may also be based on previous performance data for the particular appliance, that is, given the current conditions (e.g., various environment temperature readings), how long has it taken in the past for the appliance to reach a certain level of operation. The location of the user is determined by a device that has some location-based services and is able to transmit this location/position data in a message to a power-control server. The server applies rules contained in the message to derive an estimated arrival time for the user which is used to power appliances at the user's destination.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

Abstract: In a building equipped with a plurality of motion-enabled chairs such as a movie theatre, the vibration of the motion-enabled chairs adds up and may damage the foundation of the building especially at the resonance frequency. The present application describes a system and method for controlling the resulting vibration by introducing an alteration such as a delay or an inversion in the motion signals sent to the motion-enabled chairs. This delay causes the vibration of some motion-enabled chairs to be de-phased from the vibration of the other motion-enabled chairs. Whereby, the intensity (magnitude) of the resulting vibration is reduced. Control of the motion-enabled chairs may be done centrally through a central controller, or locally at selected motion-enabled chairs.

Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

Abstract: A cable bypass assembly is disclosed for use in providing a high speed transmission line for connecting a board mounted connector of an electronic device to a chip on the device board. The bypass cable assembly has a structure that permits it, where it is terminated to the board mounted connector and the chip member, or closely proximate thereto. to replicate closely the geometry of the cable. The connector terminals are arranged in alignment with the cable signal conductors and shield extensions are provided so that shielding can be provided up to and over the termination between the cable signal conductors and the board connector terminal tails. Likewise, a similar termination structure is provided at the opposite end of the cable where a pair of terminals are supported by a second connector body and enclosed in a shield collar.

Abstract: A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state while the audio data is being processed. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor.

Abstract: Embodiments disclosed herein relate to the field of computer technologies, and disclose a two-dimensional code processing method and a terminal, which can reduce time for a user to learn content indicated by a two-dimensional code, thereby improving a user experience effect. The method provided by the embodiments of the present invention includes: scanning a two-dimensional code using a camera to obtain two-dimensional code information, sending a first request message including the two-dimensional code information to a server, where the first request message is used to enable the server to determine description information corresponding to the two-dimensional code information; receiving the description information sent by the server; and outputting the description information, so that the user determines, according to the description information, whether to acquire detailed information corresponding to the two-dimensional code information.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

Abstract: An information processing apparatus operating in a first power state, a second power state, a third power state, and fourth power state includes a power control unit configured to the third power state to the fourth power state when a first shift time is measured, and a control unit configured to, when the power control unit has shifted the power state of the information processing apparatus from the third power state to the first power state, clear the measured time and not to, when the power control unit has shifted the power state of the information processing apparatus from the third power state to the second power state, clear the measured time clear.

Abstract: According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.

Abstract: According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

Abstract: In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

Abstract: In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.

Abstract: A socket structure includes a base; a slot, disposed on one end of the base and to be connected to one plug having one row of terminals; a tongue disposed on a front end of the base and within the slot so that chambers of the slot on two sides of the tongue may be normally and oppositely inserted and positioned into the slot; one row of first contacts separately arranged on one surface of the tongue, wherein each first contact is electrically connected to a first pin extending out of the base; and one row of second contacts separately arranged on the other surface of the tongue. Each second contact is electrically connected to a second pin extending out of the base. When the plug is inserted into the slot, the row of terminals of the plug are electrically connected to the row of first or second contacts.

Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Abstract: There is provided a system and method for detecting a distance to an object. The method comprises providing a lighting system having at least one pulse width modulated visible-light source for illumination of a field of view; emitting an illumination signal for illuminating the field of view for a duration of time y using the visible-light source at a time t; integrating a reflection energy for a first time period from a time t?x to a time t+x; determining a first integration value for the first time period; integrating the reflection energy for a second time period from a time t+y?x to a time t+y+x; determining a second integration value for the second time period; calculating a difference value between the first integration value and the second integration value; determining a propagation delay value proportional to the difference value; determining the distance to the object from the propagation delay value.

Abstract: Techniques for supporting optical and electrical protocols, such as on the ports of a line card in a network device, are provided. A port on a line card supports optical and electrical connections. The PHY monitors a signal to determine if the transmission connection at the port has changed, such as from optical to electrical, or vice versa. If there has been a change, the PHY is directed to reset a port to correspond to the appropriate transmission connection. By resetting the port, the PHY changes the protocol that is utilized with the signals (e.g., NRZI or 3-Level MLT3).