Patents Examined by Christopher Euripidou
  • Patent number: 6785841
    Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Chekib Akrout, Harm Peter Hofstee, James Allan Kahle
  • Patent number: 6782489
    Abstract: The present invention provides a system and method of detecting a process failure and a network failure in a distributed system. The distributed system includes at least two processes, each executing on a host, operable to transmit messages (i.e., heartbeats) to each other on a plurality of networks in the distributed system. A process in the system is operable to execute a network failure algorithm for detecting failure of a network in the system. The process failure algorithm includes calculating a difference in the period of time to receive a heartbeat on a first network from a process and a period of time to receive a heartbeat on a second network from the process. If the difference exceeds a network failure threshold, the second network is suspected of failing. A process in the system is also operable to execute a process failure algorithm.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: August 24, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Roger A. Fleming
  • Patent number: 6782496
    Abstract: The present invention provides a system and method of adjusting a heartbeat timeout utilized for monitoring a process in a distributed system. The distributed system includes a plurality of processes monitoring one another by transmitting messages (i.e., heartbeats) indicative of a process being operational. A first process monitoring a second process is operable to receive one or more heartbeats from the second process in the distributed system. If the first process fails to receive a heartbeat from the second process prior to an expiration of the heartbeat timeout, the second process is suspected of failing. If the first process receives a heartbeat from the second process prior to the expiration of the heartbeat timeout, the first process recalculates the heartbeat timeout. Recalculating the heartbeat timeout includes gradually increasing or decreasing the heartbeat timeout based on a period of time to receive a heartbeat.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: August 24, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Roger A. Fleming
  • Patent number: 6766478
    Abstract: A protective circuit for protecting hard disk data comprises: a first HD coupling device connected to a hard disk port of motherboard; a second HD coupling device connected to a hard disk; a HD signal processor coupled to the first HD coupling device, the second HD coupling device, and a microprocessor respectively; a random access memory (RAM) connected to the microprocessor; a nonvolatile semiconductor memory having program codes for converting a read/write instruction of the hard disk port on the motherboard with respect to the hard disk from a main data space to a virtual data space thereof; and the microprocessor for running program codes. The protective circuit can recopy the data in the main data space to the virtual data space in the case that the data stored in the virtual data space are corrupted.
    Type: Grant
    Filed: March 3, 2001
    Date of Patent: July 20, 2004
    Inventor: Kwok-Yan Leung
  • Patent number: 6754852
    Abstract: A trigger signal TRIG[0] is produced for use in debugging data processor (14) operations. The trigger signal can be generated in response to event information indicative of events associated with operations of the data processor and further in response to past behavior of a trigger signal. A plurality of intermediate terms index into a look up table loaded from a trigger builder control register. The look up table output is ANDed with output enable signals to produce plural trigger output signals.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: June 22, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 6735719
    Abstract: A method for performing load testings on software applications is disclosed. A test script is initially recorded. A location at which dynamic data are first generated within the recorded test script is then identified. Proper data correlation statements are subsequently inserted into the recorded test script. The inserted data parameters are then substituted throughout the recorded test scripts. After verifying all dynamic data have been captured and replaced, a load test is performed on a software application utilizing the recorded test script.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin LaVern Moe, Timothy Darold Vanderham
  • Patent number: 6732297
    Abstract: This invention relates to a method of generating a test-instruction string to test the pipeline mechanism of a processor, which automatically generates from randomly generated instructions an instruction string which causes a pipeline interlock. This invention comprises a table for notifying the subsequent instruction of the status of resource usage of the leading instruction and, by generating the resources used, by the subsequent instruction according to the status of resource usage of the table automatically generates a subsequent instruction that interferes with the leading instruction.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 4, 2004
    Assignee: Fujitsu Limited
    Inventor: Hironobu Oura
  • Patent number: 6721901
    Abstract: A method and system for recovering mirrored logical data volumes within a computer system after a system failure is disclosed. A computer system includes mirrored logical volumes that can be accessed by multiple nodes. Mirrored in-flight logs are provided for the mirrored logical volumes. The mirrored in-flight logs include multiple node partitions, each node partition corresponding to one of the nodes. Furthermore, each entry within the mirrored in-flight logs indicate whether or not a write operation is currently being performed by at least one of the nodes. After an abnormal termination of one of the nodes due to, for example, a system failure, one of the remaining nodes is automatically selected to copy data from one of the mirrored logical volumes to another of the mirrored logical volumes, according to the entries within one of the mirrored in-flight logs.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gerald Francis McBrearty, Johnny Meng-Han Shieh
  • Patent number: 6718485
    Abstract: The present invention is a software system that detects large classes of programming and run-time errors in a computer program by emulating the hardware platform and monitoring the execution of a program and the concurrent data manipulation. The software system locates bugs in binary object executable programs. Working on the binary object executable program at runtime, the tool verifies memory references and program implementation by monitoring each logical memory access for data.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: April 6, 2004
    Assignee: Parasoft Corporation
    Inventor: John F. Reiser