Abstract: A low cost method of producing proper source/drain junctions and transistor characteristics is disclosed. Through consolidation of masking steps, source/drain processing has a significantly lower cost with no performance loss. A blanket boron implant is employed as both a PLDD implant for the PMOS and a halo region implant for the NMOS. After formation of sidewall spacers on the gates, a masked arsenic and phosphorous implant is employed as a N+ implant. Because the phosphorous drives in faster than the arsenic, the desired N+/NLDD/halo architecture is generated. A masked boron implant is then employed as the P+ implant. Thus, the source/drain junctions are formed using only two masked implants. In an alternative embodiment, a third masked implant of phosphorous is used to form the NLDD junction prior to the sidewall spacer deposition instead of phosphorous being implanted with the arsenic.

Abstract: A method of forming an interconnection contact for integrated circuit package components includes providing an integrated circuit package component having a contact pad on which the interconnecting contact is to be formed. The interconnecting contact is formed by forming at least a portion of a bonding wire loop connected to the contact pad. A first end of a bonding wire is connected to the contact pad. The bonding wire loop includes a wire portion extending outwardly from the contact pad. The portion of the bonding wire loop forms the interconnection contact for electrically connecting the integrated circuit package component to other electrical devices. In one embodiment, a second end of the bonding wire loop is connected to the same contact pad that the first end of the bonding wire loop is connected to. In another embodiment, a second end of the bonding wire loop is connected to another contact pad.