Patents Examined by Christopher Lattn
  • Patent number: 6699782
    Abstract: A fabrication method of wafer level packages capable of improving reliability by maximizing a contact area of metal wiring and a conductive ball and of simplifying fabrication processes by reducing the number of sputtering. The disclosed method comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer including a first opening exposing the chip pad and a second opening forming a ball land on the substrate; forming metal wiring connected to the chip pad in a single unit through the first opening and covering the second opening to have a ball land on the first insulating layer; forming a second insulating layer including a third opening which covers the metal wiring, however, exposes the ball land; and adhering a conductive ball to be in contact with the third opening on the ball land.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 2, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Heon Kim