Patents Examined by Christopher M Euripidou
  • Patent number: 6772369
    Abstract: A method and mechanism for configuring a node in a computing system to route data to a predetermined observation point. A node in a computing device or system is configured to identify and convey an observation data stream via a non-critical path. A non-critical path is configured within the computer system for the transmission of the generated stream of data to a convenient client location where the data may be observed. This stream of data is routed through the computer system via disabled, replicated, monitor or other links which correspond to a non-critical path. The observation data stream conveyed by the node may be generated by the node and correspond to an internal state of the node. Additionally, the node may be configured to duplicate and convey received data streams or extract debug data from a received data stream for conveyance to a predetermined observation point.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: August 3, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian L. Smith, Jordan Silver
  • Patent number: 6772373
    Abstract: A LAN connector 30 inserted between a high level equipment 11 and low level equipment 21, and incorporating only protocols for the first layer or up to the second layer for OSI to enable the transmission of communication data between the high level equipment and the low level equipment, comprises a ROM 65 to store disorder notification patterns correspondent with possible disorders, and a disorder notification control portion 51 which monitors an upside-originated idle signal from the high level equipment 11, or a downside-originated idle signal from low level equipment 21 using the protocol for the first layer; detects a disorder involving a component of the network as well as a disorder involving the LAN connector itself based on the monitoring result of the upside- or downside-originated idle signal; reads out from ROM a disorder notification pattern correspondent with the disorder thus detected; and transmits the pattern to the high level equipment 11 via an optical cable 70.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 3, 2004
    Assignee: Hitachi Telecom Technologies, Ltd.
    Inventor: Yoshikazu Sugeno
  • Patent number: 6754850
    Abstract: A method for creating a computer program to be executed by a plurality of threads, in which the method utilizes a technique for execution synchronization referred to herein as a batch synchronization section. According to this technique, a plurality of threads may be associated with one another as a “batch” of threads. Each thread in the plurality (batch) of threads may execute the computer program simultaneously. The batch synchronization section may specify a portion of the computer program for which the execution of the portion by the plurality of threads is to be synchronized. In one embodiment different types of batch synchronization sections may be specified, wherein each type of batch synchronization section performs a different type of execution synchronization. In one embodiment the method may enable execution synchronization behavior for multiple concurrent executions of a test executive test sequence to be specified.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: June 22, 2004
    Assignee: National Instruments Corporation
    Inventors: James Grey, Douglas Melamed, Jon Bellin
  • Patent number: 6745346
    Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 1, 2004
    Assignee: Intel Corporation
    Inventors: Nhon T. Quach, Amy L. O'Donnell, Asit K. Mallick, Koichi Yamada