Abstract: A multistage network having a combination of low latency and probability of blockage has particular application in the interconnection of parallel computers. A technique minimizes the blockage of the multistage network, thereby minimizing the number of times that a message requires retransmission. The technique also permits higher utilization of data transport paths in the multistage network. The network has no buffers, so a message either succeeds in getting through, or, if blocked, leads to the notification of the originator that transmission was unsuccessful and that another attempt is required. Multiple return paths, used for example in a time-division-multiplexed (TDM) fashion, are provided in the network. This substantially reduces the amount of blocking in the network, and thus the number of times that a message requires retransmission. In addition, networks associated with the backward paths are used as a means of controlling the data transport.

Abstract: A pulse duration multiplexing communication system wherein the data pulse durations are defined as a function of the system clock tolerance. This results in no overlapping of data pulse durations for any local clock operating within the tolerance range.

Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.

Abstract: A method and device are provided for the asynchronous transmission of data packets, consisting in transmitting messages in the asynchronous mode, the messages comprising a beginning of message character, a character designating the address of the addressee, possibly a character designating the address of the sender, possibly characters containing the significant information of the message, and an end of message character. The beginning of message and end of message characters are formed of a continuous pulse of a length equal to the number of the significant bits of a normal message character increased by two bits. Such a pulse is recognized by the frame control circuits, in the case where the characters are without parity bits; they are recognized by the parity control signals in the case where the characters are provided with parity bits.

Abstract: A transmission system in which a plurality of data streams are to be multiplexed and sent between receiving and transmitting equipment. At the transmit end the system comprises a plurality of worker tributary cards (51, 52) each having an input port (57) connected to an individual tributary to be sent to an associated multiplexer, and a stand-by tributary card (56) operative to replace a failed worker card. All the worker tributary cards (51-55) are interconnected by a common line (60) leading to the iput port (57) of the stand-by tributary card (56) but in normal operation being isolated from said line by a controllable unity-gain buffer 58.

Abstract: A signalling transmission system is disclosed which consists of a transmitting module including a signalling variation detecting unit and a signalling synthesization unit, and a receiving module including a signalling flag detecting unit and a signalling separation unit. The signalling synthesization unit makes composition signals by inserting signalling signals into voice signals together with a flag when signalling variations are detected by the variation detecting unit. A flag detecting unit detects a flag contained in the composition signals received by the receiving module and instructs the separating unit to separate the signalling signals from the voice signals contained the composition signals when the flag shows that the composition signals include the signalling signals. The signalling signals and the voice signals are therefore output from the receiving module.

Abstract: The invention provides a telecommunications system exhibiting an architecture having a plurality of functional levels decoupled from one another by data transport systems. The communication facilities connected to the periphery of the system are terminated at the physical level only and the data is channelized for transmission through a channel switch to a first level of processing that provides channel services. The data is then multiplexed and transmitted to system and call processing resources via a frame transport system.

Abstract: A data link (1000) multiplexes a large number of concurrently operating channel onto a single pair of fiber-optic cables (10 and 1010). A receiver (1004A) at one end of the links determines whether it is in sychronism with the signals that it receives over one of the cables (1010), and a transmitter (1002A) includes the result of that determination with the data that it sends to the other end if the link so that devices at the other end of the link can be caused to log off in response to extended lapses in synchronism at the first end. Each transmitter also sends an error count to the other end, and is responsive to a mode signal from the other end to reduce its signal power, so that maintenance personnel can perform many testing and diagnostic procedures from a single end of the link.

Abstract: A single international standard integrated services digital network (ISDN), basic rate interface (BRI) is arranged so that either a data terminal and two voice terminals, three voice terminals, or four voice terminals can be operated simultaneously through the interface. Code converters, associated with the voice terminals and with a central office switch, convert eight-bit voice sample code from either the voice terminals or the central office switch to four-bit voice sample code in the interface to enable the bit streams of two voice terminals to be merged for transmission through a single B-channel at the interface. When two voice terminals are operated simultaneously through one B-channel, each of those terminals positions four-bit coded voice samples in a different sub B-channel of the B-channel and stuffs four bits in the other sub B-channel.

Abstract: A D channel monitor is provided which is capable of providing a plurality of operating modes for monitoring D channel operation. As such, the D channel monitor can include first and second interface elements which can be operated to appear as either an NT interface (for a TE) or as a TE interface (for an NT). A controller is provided which can control the first and second interface elements to appear as predetermined ones of the NT interface or the TE interface for respectively coupling to either a TE or an NT of the ISDN user terminal. A monitoring arrangement is also included for monitoring the D channel signals at the terminal which are received through either of the first and second interface elements. This monitoring arrangement includes means for indicating the status of the D channel signals to a user.

Abstract: A power saving method and apparatus in a time division multiplexed system (10) capable of providing a synchronous full duplex communication between a telephone network (12) and a plurality of remote communication units (18). A communication resource controller (14) provides system synchronization, by periodically trnsmitting synchronization messages through one or more remote sites (11). The communication units (18) attempt to acquire synchronization during a synchronization acquisition interval. If synchronization is acquired, the communication units (18) enter a synchronous battery saving mode (515). In the synchronous battery saving mode (515), the communication units (18) can detect a call request either to their own address or to the address of another communication unit. If no call request is detected, the communication units (18) reduce power consumption for a synchronous power saving time interval, and thereafter merely verify synchronization.

Abstract: A low speed channel bypass apparatus is described for reprovisioning the time slot multiplexer associated with an add/drop multiplexer so as to insure that particular low speed channel(s) within a high speed channel are passed through the add/drop multiplexer via the time slot multiplexer when the operation of an associated network controller is determined to be faulty. The low speed channel bypass apparatus is particularly directed for use with a high speed channel conforming to the synchronous optical network communication standard (SONET). A watchdog timer is used to monitor the performance of the network controller. The watchdog timer when timed out not only prevents further operation of the network controller, but instructs an associated reprovisioning apparatus to instruct the time slot multiplexer to connect through selected channel(s) from the east high speed interface to the west high speed interface.

Abstract: A method by which the each module of a token passing local area network complying with IEEE standard 802.4 determines if the communication cable from which it is receiving signals is faulty and switches to a second, or redundant cable. Each module transmits the same signals over both cables, but can receive signals from only one, its selected cable. In normal operations, all modules receive signals from the same cable. Each of the modules has the capability of detecting faults in its selected cable, and of switching cables so that its second cable becomes its selected cable. Each module also has the capability of initiating the process or re-establising the network whenever a module switches cables in response to detecting a fault. Each module in response to the process of initiating re-establishing the network, switching cables so that all modules are listening to, or receiving signals from the same cable.

Abstract: A system for transmitting digital data by time division multiplex (TDM) includes a transmission terminal for transmitting a TDM data stream having a frame structure which includes fixed stuff bytes and/or frame overheads forming part of the payload but not normally available to the user. The system includes a processor for locating said fixed stuff bytes, and overwriting at least some of the fixed stuff bytes to introduce mark parity, and a receive terminal having a processor for detecting the introduced parity bytes and determining whether or not there has been an error in transmission. The processor at the receive terminal includes an AND-gate to which the transmitted TDM signal containing mark parity is fed, a clock for supplying a clock signal to the AND-date, a bistable flip-flop connected to the output of the AND-gate, and a band pass filter for filtering the output of the AND-gate.

Abstract: A phase modulation system includes a phase mapping circuit (218) for mapping binary data into a plurality of discrete phase values in accordance with a predetermined phase modulation scheme. The discrete phase values are then filtered in the phase domain by a filter (220) to provide a filtered output. This filtered output is then digitized and input to a numerically controlled oscillator for phase modulating a carrier.

Abstract: Two separate switching systems, a first one for switching packet oriented data and a second one for switching circuit oriented data as known from the state of the art can, according to the invention and with regard to their function, be integrated into a single switching system. This is realized by storing the packet oriented data in a first section of a switch memory (33) and the circuit oriented data in a second section of this same switch memory (33).With this realization additional advantages occur such as a movable boundary in the switch memory (33) between the packet oriented section and the circuit oriented section and a saturation monitoring that can be realized in a simple fashion in the switch memory (33).

Abstract: A unique packet transport word, i.e., header, format is disclosed which is advantageously employed to delimit the corresponding packet and to verify data fields in the transport word. An at least first parity check is employed in conjunction with a packet length indicator to delimit the corresponding packet. The at least first parity check is formed by computing a predetermined number of parity check bits from bits in predetermined bit positions of the transport word. These parity check bits are inserted into predetermined bit positions in the transport word. Similarly, bits representing the packet length indicator are also inserted into predetermined bit positions of the transport word. In a specific embodiment, a plurality of parity checks is employed to achieve increased robustness. The plurality of parity checks is formed such that each of the bits in predetermined bit positions of the transport word is used in computing at least two different parity check bits.

Abstract: The present invention relates to a system which uses information in a certain band of frequencies, f.sub.b. The information of interest is contained in an analog signal that has noise at higher frequencies. The analog signal is sampled using an integrate and hold amplifier, hence, noise from higher frequencies is aliased into the region of interest f.sub.b. In accordance with the present invention, the integrated and hold amplifier has a frequency response which has a zero at a frequency, f.sub.n, which is one of the frequencies aliased into the band of frequencies f.sub.b. Thus, the effect of the noise that appears near the frequency f.sub.n has much less effect on the signal when it is aliased into the frequency band of interest, f.sub.b. The performance of the system is thereby improved.

Abstract: A peripheral controller for a PBX system accepts PCM data from a plurality of channels. The channels may be processed in time and space switches of more than one network loop. A channel-merge device merges the PCM data into a combined PCM data stream for connection to a time switch. The time switch is controlled by a connection memory to direct data on specific channels to specific terminals.

Abstract: Data multiplexing system for dispatching an input serial bit stream onto a plurality of ports, or multiplexing the data bits received from a plurality of ports as a serial bit stream. The system mainly comprises for each port, a mask register (14) loaded with a N-bit mask work wherein bits set to 1 indicate which bits of an aggregate register (10 or 56) are to be loaded or to be transferred, and a scan counter (20 or 46) starting being incremented at a high frequency at each transition of a first category, up or down, of a clock circuit (12 or 40), until the mask bit corresponding to the scan counter contents is a bit 1, whereby the corresponding cell of the aggregate register is transmitted to the associated port or loaded with the bit received at this time by the associated port.