Abstract: A computer system having a bus, a bus master, and a plurality of semiconductor devices having bus transaction response characteristics that are configurable by the bus master via the bus. Each semiconductor device includes at least one register that is operative to store information specifying a manner in which the semiconductor device is to respond to transaction requests received from the bus. The bus master transmits the information to the semiconductor device via the bus lines of the bus when the bus in configured. The semiconductor device stores the information received from the bus lines in the register during configuration of the bus and thereafter responds to requests according to the information stored in register. Configurable bus transaction response characteristics may include a unique device identification for the semiconductor device, a range of addresses to which the semiconductor corresponds, or the bus access-time of the semiconductor device. The semiconductor device may be a memory device.