Patents Examined by Chun-Kuan Lee
  • Patent number: 10802540
    Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a location-based power saving solution for docking station products. A wireless docking station communicates with a docking wireless device. The docking station is activated when the docking wireless device when the docking wireless device is within a pre-configured coverage area of the docking station. The docking station is deactivated when the docking wireless device when the docking wireless device is outside the pre-configured coverage area.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel IP Corporation
    Inventors: Timor Israeli, Eduard Kvetny, Lior Yeheskiel
  • Patent number: 10776122
    Abstract: Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Eula Faye Abalos Tolentino, Dung Q. Nguyen, Jeffrey C. Brownscheidle, Tu-An T. Nguyen, David S. Walder
  • Patent number: 10761744
    Abstract: Provided are techniques for synchronously performing commit records operations. A local copy of a commit records message is built for a Non-Volatile Storage (NVS) track, with a valid indicator set to indicate that this commit records message is valid and has not been processed yet. A Direct Memory Access (DMA) chain is executed to transfer customer data from a host to real segments and alternate segments of a track buffer and to transfer the local copy of the commit records message to a mail message structure of a mail message array. At DMA completion, an NVS manager is synchronously called to perform a commit records operation with the commit records message in the mail message structure. In response to the commit records operation completing, there is an indication that a new write DMA is allowed to proceed for the NVS track.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson, Louis A. Rasor
  • Patent number: 10740108
    Abstract: Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10732981
    Abstract: Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10732979
    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 4, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Marius Evers, Aparna Thyagarajan, Ashok T. Venkatachar
  • Patent number: 10725958
    Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Anitha Kona, Mark David Werkheiser
  • Patent number: 10719319
    Abstract: In one embodiment, a processor comprises a decoder to decode a first instruction, the first instruction comprising an opcode and at least one parameter, the opcode to identify the first instruction as an instruction associated with an indirect branch, the at least one parameter indicative of whether the indirect branch is allowed; and circuitry to generate an error message based on the at least one parameter.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Kekai Hu, Ke Sun, Rodrigo Branco
  • Patent number: 10698687
    Abstract: An example system includes a plurality of execution units, a shared resource, and an allocation control circuit. Each execution unit may generate a resource allocation request that includes a resource allocation size. The allocation control circuit may select a particular resource allocation request from the plurality of resource allocation requests, and determine an availability, based on an allocation register, of contiguous resource blocks within the shared resource. In response to determining that a number of the contiguous resource blocks satisfies a requested allocation size, the allocation control circuit may select an address corresponding to a particular resource block of the one or more contiguous resource blocks, and allocate the resource blocks to a corresponding execution unit. In response to a beginning of a second system clock cycle, the allocation control circuit may also update the allocation register based on the selected address and the requested allocation size.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Dimitri Tan, Jeffrey T. Brady, Terence M. Potter, Jeffrey M. Broton, Frank W. Liljeros
  • Patent number: 10684611
    Abstract: An industrial control I/O module for interfacing with industrial control equipment, such as sensors and actuators, can be configured to dynamically provide differing resistances in each channel as may be required for reliably achieving particular modes of operation in the channel. Providing differing resistances in such channels flexibly allows different modes in the channel to provide universal I/O capability. Modes of operation could include, for example, digital output, digital input, analog output, analog input and the like, in the same channel, but at different times. In one aspect, a processor or voltage divider can be used to control an amplifier, with feedback, driving a transistor in a channel to dynamically adjust resistance in the channel by selectively biasing the transistor to achieve a resistance in the channel suitable for the selected mode.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 16, 2020
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: John R. O'Connell, Rajesh R. Shah
  • Patent number: 10664425
    Abstract: A processor may include a core to execute interrupt latency control unit (ILCU) software and an interrupt controller circuitry. The interrupt controller circuitry includes: a first register to store a first time value at which a first interrupt is received at the interrupt controller circuitry and a second register to store a second time value at which the first interrupt is delivered to the core. The ILCU software is to: read the first time value in the first register and the second time value in the second register; determine an amount of time the first interrupt was pending at the interrupt controller circuitry; determine interrupt configuration information that adjusts the first interrupt priority of a subsequent interrupt; and send the interrupt configuration information to the interrupt controller circuitry. The interrupt controller circuitry is to adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventor: SampathKumar Malalangaradhos
  • Patent number: 10642769
    Abstract: SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 5, 2020
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Wes Vernon Lofamia, Jofrey Santillan, David Aherne
  • Patent number: 10628209
    Abstract: Provided is a virtual interface, a “Forwarder” and a Virtual Block Storage Device (VBSD). The virtual interface is the interface between a Command/Response Queue (CRQ), which receives CRQ commands from a virtual machine monitor, and a common interface of the Forwarder. The Forwarder receives I/O commands in a format associated with the common interface and converts the commands into a generic I/O format. The reformatted command is transmitted to the VBSD. The virtual machine monitor sends a read or write (R/W) request to the virtual interface, which passes the request to the Forwarder. The Forwarder receives the request, converts the request into a form readable by the VBSD and transmits the converted request to the VBSD. The VBSD transmits the request to a block storage device and returns the response to the Forwarder. The Forwarder replies to the request from the virtual interface with the response from the ABSD. The virtual interface then responds to the virtual machine monitor.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jorge R. Nogueras, Morgan J. Rosas, James Y. Wang
  • Patent number: 10614009
    Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, Helena Deirdre O'Shea, Wolfgang Roethig, Christopher Kong Yee Chun, ZhenQi Chen, Scott Davenport, Chiew-Guan Tan, Wilson Chen, Umesh Srikantiah
  • Patent number: 10592457
    Abstract: A universal transponder interface including: a compartment configured to store a vehicle ignition key; a docking station configured to receive a databus cartridge, wherein the databus cartridge includes codes to support a plurality of different types of databus communication; a first interface configured to connect the universal transponder interface to a vehicle databus; and a second interface configured to connect the universal transponder interface to a vehicle security or remote start system.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: March 17, 2020
    Assignee: VOXX INTERNATIONAL CORPORATION
    Inventors: Joseph Dentamaro, Joseph Santavicca, Shane Wilson
  • Patent number: 10579267
    Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: March 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuaki Takeuchi, Yoshihisa Kojima, Norio Aoyama, Mitsunori Tadokoro
  • Patent number: 10572409
    Abstract: A memory arrangement can store a matrix of matrix data elements specified as index-value pairs that indicate row and column indices and associated values. First split-and-merge circuitry is coupled between the memory arrangement and a first set of FIFO buffers for reading the matrix data elements from the memory arrangement and putting the matrix data elements in the first set of FIFO buffers based on column indices. A pairing circuit is configured to read vector data elements, pair the vector data elements with the matrix data elements, and put the paired matrix and vector data elements in a second set of FIFO buffers based on column indices. Second split-and-merge circuitry is configured to read paired matrix and vector data elements from the second set of FIFO buffers and put the paired matrix and vector data elements in a third set of FIFO buffers based on row indices.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 25, 2020
    Assignee: XILINX, INC.
    Inventors: Jindrich Zejda, Ling Liu, Yifei Zhou, Ashish Sirasao
  • Patent number: 10565148
    Abstract: A system and method for configuring a filter object for a controller area network is disclosed. The method includes determining, by a processor, a plurality of message identifiers of messages that are to be captured by a filter object. The method also includes performing factorization of a function that represents the plurality of message identifiers to generate a simplified function. The method also includes configuring at least one filter object based on the generated simplified function.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 18, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Paolo Giusto, Grant A. Soremekun, Michael A. Turley, Ramesh S
  • Patent number: 10540096
    Abstract: A method of managing memory descriptors for a plurality of commands to a non-volatile semiconductor storage device includes requesting memory descriptors from a host system for each of the plurality of commands stored in a first memory, storing the memory descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a second memory of the non-volatile semiconductor storage device, and maintaining a dynamic descriptor list in the second memory for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the second memory having associated memory descriptors. At least one of the occupied descriptor regions includes multiple memory descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Sancar Kunt Olcay
  • Patent number: 10534729
    Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: January 14, 2020
    Assignee: XILINX, INC.
    Inventors: Pongstorn Maidee, Theepan Moorthy