Patents Examined by Chung My Phung
  • EEPROM verification circuit with PMOS transistors
    Patent number: 5550842
    Abstract: The present invention provides a verification circuit for EEPROM cells by connecting PMOS verify transistors in parallel across the EEPROM cells to be tested. This configuration occupies less space on a PLD chip than prior verification circuits and allows all EEPROM bits associated with one logic cell in the PLD to be coupled to one verify path, minimizing logic complexity.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 27, 1996
    Assignee: Altera Corporation
    Inventor: Nghia Tran