Abstract: The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed in a substrate, removes a cap layer formed on each of a plurality of gate stacks formed on the substrate to expose an upper surface of each of the gate stacks, forms one or more contact holes in the bulk insulation layer to expose a portion of one or more of the source/drain regions, and forms control gates and one or more contacts concurrently by forming a conductive layer on the exposed upper surface of each of the gate stacks to form the control gates and in the one or more contact holes to form the one or more contacts.

Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.