Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.
Type:
Grant
Filed:
November 29, 1994
Date of Patent:
November 12, 1996
Assignee:
Board Of Regents, The University Of Texas System
Abstract: A digital divider for forming the quotient (Q) of two numbers (A,B) includes means providing values (Q+1, Q-1) of the quotient with possible rounding errors added to or subtracted therefrom.
Abstract: A method for utilizing a cyclical redundancy check value with an identification field stored in memory which is constantly changing between testing of the cyclical redundancy check value. In order to allow the use of a cyclical redundancy check value with a field which constantly varies as does the field in a flash EEPROM memory array, various portions of the field are masked to the cyclical redundancy check and additional reliability checks are utilized to assure that those portions which are masked remain reliable.
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