Patents Examined by Chuong Lee
  • Patent number: 6258720
    Abstract: The present invention relates to a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined width at the locations where the conductive line is to be formed; depositing and etching a first interconnection layer of a first thickness; and depositing and etching a second interconnection layer of a second thickness; the predetermined width being higher than twice the greatest of the two thicknesses, and lower than twice the sum of the thicknesses.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 10, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Yvon Gris