Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory device can include memory cells. The processing device can store operation system data in the memory cells in a single level cell (SLC) mode. The processing device can assert a flag indicating that the data written to the memory cells in the SLC mode is to remain stored in the SLC mode. The processing device can de-assert the flag, thereby indicating that the data is foldable into memory cells in a non-SLC mode.

Abstract: A memory control method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit in response to a first read command from a host system; performing a first decoding operation on the first data to obtain decoded data corresponding to the first data; storing the decoded data corresponding to the first data in a buffer memory; reading second data from the first physical unit in response to a second read command from the host system; performing a second decoding operation on the second data; and in response to failure of the second decoding operation, searching the buffer memory for the decoded data corresponding to the first data to replace the reading of the second data.