Abstract: A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.
Type:
Grant
Filed:
June 10, 2005
Date of Patent:
July 8, 2008
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Kai Frohberg, Matthias Schaller, Joerg Hohage, Holger Schuehrer
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