Abstract: A method and an apparatus for dynamically determining the optimal communication mess age bundle size for a communications system based on system resource utilization parameters, such as CPU utilization, message processing latencies, and paging message response delays within the system. At low loads, a bundle size of 1 message is selected. Under such conditions, paging messages are broadcast to mobile units in real time, with no waiting. As the mobile station termination activity increases and the round-trip-paging response delay exceeds a threshold, the bundle size is increased to reduce the processing overheads, which, in turn, reduces the end-to-end system delay for paging. As the paging message traffic decreases, the bundle size is reduced to decrease the delay introduced by bundling, which, in turn, reduces the round-trip-paging response delay.

Abstract: A digital transmission system comprising a receiver, the receiver including a receiver input stage and a digital memory for storing a sequence of binary symbols of sample values, formed in the receiver input stage, of a signal distorted by a transmission channel, and an equalizer for forming a sequence of binary estimates from the sample values by an impulse response of a substitute system describing the transmission channel, the impulse response being determined by first correlations of coefficients of a known training sequence with the sample values of a part of the known training sequence extended by at least one binary symbol.

Abstract: This invention relates to telecommunications systems. In a subscriber loop carrying high speed data signals, noise cancellation is achieved by a data signal demodulator having first and second inputs 81,82, arranged to receive differential data signal and local field RFI input signals respectively. A feedback signal of the demodulator is sampled, processed, vector modulated and then combined with the local field RFI input signal of the demodulator. The combined signal is summed with the differential input signal to thereby reduce interference coupled with the first input.

Abstract: A decoding circuit for a magnetic recording and reading system enables the implementation of an AGC loop with a relatively simple configuration and further enables easy clock extraction and high operating speed. The level setting system for setting the signal level to be taken as the value 1 in the decoding circuit is configured so as to comprise a variable-gain amplifier, a PR4 equalizer having characteristics capable of equalizing to a target PR4 equalization waveform, and a level detector which feeds the output signal back to the variable-gain amplifier as an AGC loop control signal to control the gain thereof. The detection system of the decoding circuit is configured so as to comprise a VFO which generates a system clock fs, and a decision feedback type decoding means in a decision section, which decodes data lines which appear at the output of the PR4 equalizer.

Abstract: In digital transmission systems, such as synchronous transmission systems according to the SDH/SONET standard, there is a need to have information on the synchronization status of the system. A known approach is to monitor the pointer activity. This is disadvantageous in that because of a hysteresis in the pointer processor, information derived from the pointer activity only conditionally reflects the synchronization status. In a network element (1) according to the invention which forms part of a transmission system of the above type, at least one interface unit (2, 3, 4) contains, besides an optical-to-electrical transducer (5), a synchronization-monitoring device (6) which derives a synchronization status parameter, e.g., TIE, RMSTIE, by comparing an external clock frequency (T.sub.e) with an internal clock frequency (T.sub.i). For this, the synchronization-monitoring device (6) comprises a phase-comparing device (37), a memory device (25), and an evaluating device (26).

Abstract: A delayed detection MRC diversity circuit which does not adjust synchronization in every reception branch independently having a simple circuit constitution and superior receiving characteristics. The delayed detection MRC diversity circuit is composed of a comparison circuit for selecting a reception branch with maximum RSSI, a selector, a base band circuit such as synchronous circuit and so forth for generating a regenerative clock while adjusting bit-synchronization in terms of the reception branch with the maximum RSSI, and a MRC diversity circuit section for composing using the regenerative clock.

Abstract: In a receiving apparatus for spread spectrum communications, a carrier detecting circuit for detecting a carrier in a spread spectrum modulated signal is intermittently operated in a standby mode.

Abstract: An error correction code is a code of n+1 bits which is obtained by applying a predetermined calculation onto data of n bits and attaching a redundant bit, for example. The error correction code can correct errors generated by itself during transmission. However, when "step out" from n+1 bits interval or asynchronous state occurs, the error correction code becomes unable to correct errors. This invention detects the "step out" of the error correction code using a syndrome, carries out a bit shifting on the data and restores synchronization to the error correction code. When data series are continually transmitted as for facsimile image signals, the resynchronization apparatus of this invention is effective.

Abstract: Interference on a differential signal received at a first input to a digital data system processor is minimised or cancelled by summing a weighted portion of a local field signal with the differential signal. The local field signal may be a common-mode signal from the same line as the differential signal received at a second input. Weight may be a complex weight which shifts the local field signal in amplitude and phase. A weight control signal is derived from a comparison processor which compares the processed outputs of signal processors. Signal processors are preferably Discrete Multi-tone processors. Several iterations of this technique may be performed to establish an accurate weighting value.

Abstract: A phase-locked loop implemented in all-digital components uses a stochastic approach to detect errors in phase position and relative velocity. Using a history circuit and an adjustment-intensity selection circuit appropriate corrections in phase and frequency are made. The history circuit keeps a running record of a series of binary results (0 or 1) as received from a phase comparator. History components collected include the number of consecutive oscillator periods in which the phase offset (0 or 1) has remained the same and the number of oscillator periods in which the phase offset count has not exceeded 1.

Abstract: An automatic frequency control loop structure utilizes a dual selection automatic frequency control unit which is coupled to a differential phase unit and a coherent phase unit to provide a frequency corrected received signal output for efficient tracking of frequency offset drift and a much lower probability of loss of automatic frequency control loop lock. Thus, a signal from a coherent carrier recovery process provides additional benefit by utilization in adjusting frequency offset tracking performance.

Abstract: A receiver for a LAN which uses a transformer for isolation. Base line wander is prevented by use of a positive feedback path which provides a signal that compensates for low frequency loss through the transformer. The feedback path connects the output of the receiver to the secondary winding of the transformer. The time constant of the transformer and terminating resistor L/R equals the RC time constant in the feedback path.

Abstract: A system for detecting an underrun condition in a block processing modem and upon detection retransmitting previously transmitted data or a fixed pattern of data. The system has a register or memory location that counts the symbols in a buffer located between the microprocessor and the DSP. As a symbol is added to the buffer by the microprocessor, the register is incremented. As a block of symbols is taken from the buffer by the DSP, the register decremented. Thus at any point in time, the register contains a count of the symbols in the buffer. When The DSP is ready for a next block of symbols, logic in the DSP compares the symbol count in the register and if the count is too low for the block of symbols to be passed to the DSP, the DSP itself sends either the previous set of data or a fixed pattern of data to the AFE. The error detection software operating in the software layer above the data pump detects an error and requests a retransmission.

Abstract: The invention relates in particular to a method of compensating differences in group propagation times between first and second analog filters of a transmitter of signals in phase quadrature, and between third and fourth analog filters of a receiver of signals in phase quadrature. The method consists in: applying the output signals from the first and second filters respectively to the third and fourth analog filters so as to measure a time difference .DELTA.1 equal to: ?Tx+Rx!-?Ty+Ry! where Tx, Rx, Ty, and Ry are respective propagation times for the signals through the first, second, third, and fourth filters; applying the output signals from the first and second filters respectively to the fourth and third analog filters so as to measure a time difference .DELTA.2 equal to: ?Ty+Rx!-?Tx+Ry! and determining weighting coefficients from the differences .DELTA.1 and .DELTA.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A high speed telemetry system for implantable devices such as a pacemaker includes a transmitter disposed in an implantable housing and an external receiver. Typically the housing is metallic and it attenuates drastically electromagnetic signals having frequencies above a relatively low cut-off frequency. The transmitter includes circuitry for generating cosine waves of different frequencies and for selectively assembling these waves to define a set of data symbols. Preferably one of the frequency is a multiple of the other. Integer halve-periods of the waves are selected to define the symbols such that the overall data transmission rate exceeds the cutoff frequency. The external receiver synchronizes itself to the transmitter, and decodes the symbols using a constellation chart to decode the symbols into binary data.

Abstract: In a Global Positioning System (GPS) receiver, a significant improvement in the detection of GPS data in the presence of high interference levels is provided. In the receiver, data from multiple frames of GPS data are stacked in a memory. The stacked data is then utilized to determine the GPS data.

Abstract: The jitter of a serial digital signal is measured by determining a recurrent time window and generating a measurement ramp for each window for which the amplitude of the ramp grows proportional to the positive transition of the digital signal. The amplitude of the ramps at the end of each recurrence of the time windows is converted to digital valves and the digital values are used to calculate jitter.

Abstract: In a receiving apparatus for spread spectrum communication including a plurality of correlator elements for calculating correlation values between a plurality of bits of a spread spectrum signal and a spread reference code, all the correlator elements are operated in a signal reception mode, and only a portion of the correlator elements are operated in a standby mode.

Abstract: There is an equalizer or a receiver including an equalizer which has means to factor detected symbols transmitted over a transmission channel into a magnitude portion and a repetitive phase portion. The receiver further has means to generate modified tap weights by multiplying the repetitive phase portion by tap weights representative of the channel. Modified tap weights are generated by multiplying the repetitive phase portion by tap weights representative of the channel. The modified tap weights are convolved with bits of possible states to generate possible transmitted symbols. A maximum likelihood sequence estimation is performed on the possible transmitted symbols comparing each possible transmitted symbol to a received symbol to generate an MLSE detected symbol. The detected symbol is multiplied by a rotating vector to generate a decoded symbol.