Abstract: Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

Abstract: There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

Abstract: Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.

Abstract: Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

Abstract: An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

Abstract: The present disclosure provides a semiconductor device that includes a housing having an internal space, at least one semiconductor chip arranged inside the housing, and a separator arranged inside the housing and configured to separate the internal space of the housing into a first chamber and a second chamber. The at least one semiconductor chip is arranged within the first chamber. The separator includes a deformable portion that is configured to deform when a pressure difference between the first and second chambers exceeds a threshold differential pressure or when a temperature at the deformable portion exceeds a threshold temperature, so as to transform the first chamber from a hermetically sealed chamber to an open chamber in fluid communication with the second chamber.

Abstract: A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly comprises a semiconductor device and a cold plate directly bonded to a backside of the semiconductor device. The first side of the cold plate includes coolant channels, and a second side of the cold plate comprises at least two openings, defined by opening sidewalls extending away from the second side and towards the first side. The cavity sidewalls and the coolant channels of the first side run in a first direction, the at least two openings on the second side run in a second direction different from the first direction and overlap with portions of the coolant channels on the first side to form a continuous aperture between the second side and the first side of the cold plate.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions.

Abstract: A method for producing a superconducting vanadium silicide on a silicon layer includes treating a face of the silicon layer in order to prepare it for a deposition of vanadium silicide, then depositing a vanadium silicide layer on the prepared face of the silicon layer in order to obtain a stack of a vanadium silicide layer directly deposited on the silicon layer, then an annealing the stack which increases the critical temperature of the vanadium silicide deposited. The treating includes an operation of incorporation of argon atoms in the silicon layer through the face of the silicon layer.

Abstract: An interposer that enables implementation of a flip-chip die in a wirebonded chip-and-wire circuit assembly includes an insulating substrate having a solder bump pad array on its upper surface that is compatible with the solder bump array of a flip-chip die. Wirebond pads provided along upper edges of the substrate are interconnected to at least some of the solder bump pads. Bonding the interposer to the circuit assembly housing floor, or through an opening to an underlying motherboard, places the wirebond pads proximate attachment points of adjacent wirebond dies, enabling wirebonding therebetween. Attachment pads on the interposer lower surface, in combination with interconnecting traces and vias, can enable connection directly through the housing opening to the underlying motherboard. Support components can be included within an edge cavity created beneath an overhang of a multi-layer substrate. A heat absorbing plate can be attached to the top of the flip-chip die.

Abstract: A semiconductor device includes a substrate comprising a first interconnection configured to provide a first reference voltage, a second interconnection configured to provide a second reference voltage different from the first reference voltage, and at least one interconnection layer. The first interconnection comprises a plurality of first interconnection components that are provided in the interconnection layer. The second interconnection comprises a plurality of second interconnection components that are provided in the interconnection layer. The plurality of first interconnection components and the plurality of second interconnection components are alternately arranged in a first direction parallel to the interconnection layer.

Abstract: A method of manufacturing micro devices includes: preparing a GaN-based epitaxial structure including a p-type GaN layer, a n-type GaN layer on the p-type GaN layer, and an undoped GaN layer on the n-type GaN layer; forming a photoresist layer on the GaN-based epitaxial structure with the undoped GaN layer contacting the photoresist layer; patterning the photoresist layer; performing a plasma etching process to the GaN-based epitaxial structure through the patterned photoresist layer until the patterned photoresist layer is completely removed, such that a plurality of mesas are formed on the etched GaN-based epitaxial structure, in which a height of the mesas is at least 1.0 ?m; and continuing to perform the plasma etching process until the undoped GaN layer is completely removed and the etched GaN-based epitaxial structure is cut into a plurality of micro devices.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.

Abstract: A semiconductor device includes a substrate including cell and peripheral regions. Landing pads and contact plugs are on the cell and peripheral regions, respectively. A first filler pattern fills regions between the landing pads and between the contact plugs. Outer voids are in the first filler pattern and include first and second outer voids on the cell and peripheral regions, respectively. A second filler pattern covers the first filler pattern and the contact plugs and fills at least a portion of the second outer void. An inner void is in the second outer void and enclosed by the second filler pattern. The first and second filler patterns include the same material. On the cell region, at least a portion of the second filler pattern is located below top surfaces of the landing pads, and a bottom surface of the second filler pattern is partially exposed by the first outer void.

Abstract: A semiconductor device includes a front-end-of-line (FEOL) layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.