Patents Examined by Corey S Faherty
  • Patent number: 11372967
    Abstract: A control flow attacks based on return address signatures comprises: using a return address as a push return address when a response is given to an interrupt service routine; generating an encrypted push return address by an XOR encryption circuit by means of an n-bit binary key generated by a pseudo random number generator; then, generating a push_address signature value by an MD algorithm signature circuit; when the response to the interrupt service routine is over, reading an n-bit binary address out of a stack to serve as a pop return address; generating an encrypted pop return address by the XOR encryption circuit; generating a pop address signature value by the MD algorithm signature circuit; comparing the push_address signature value with the pop address signature value; and determining whether or not a data processor is under a control flow attack according to a comparison result.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Wenzhou University
    Inventors: Pengjun Wang, Yunfei Yu, Jiana Lian, Gang Li, Bo Chen, Yuejun Zhang
  • Patent number: 11366671
    Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 21, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak K. Singh
  • Patent number: 11366665
    Abstract: Microcode combination of complex instructions is shown. A microprocessor includes an instruction queue, an instruction decoder, and a microcode controller. The instruction decoder is coupled to the instruction queue. The microcode controller is coupled to the instruction decoder and has a memory. The memory stores a combined microcode for M complex instructions arranged in a specific order, where M is an integer greater than 1. When the M complex instructions in the specific order have popped out of the first to M-th entries of the instruction queue, the instruction decoder operates the microcode controller to read the memory for the combined microcode with microcode reading trapping happened just once.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 21, 2022
    Inventor: Yingbing Guan
  • Patent number: 11360767
    Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11360772
    Abstract: Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 14, 2022
    Inventors: Alper Buyuktosunoglu, David Trilla Rodriguez, John-David Wellman, Pradip Bose
  • Patent number: 11360775
    Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Gregory W. Alexander, Dung Q. Nguyen
  • Patent number: 11354571
    Abstract: An integrated circuit (IC) implements an L by M by N three-dimensional aperture function throughout a P by R by C three-dimensional source array. The IC has an input port receiving an ordered stream of independent input values from the source array, an output port producing an ordered stream of independent output values, an array of n compositor circuits, where n=L×M×N, each compositor circuit implementing a sub-function of the aperture function, dedicated pathways between the compositor circuits, delay circuits on the IC receiving values on the dedicated pathways from individual ones of the compositor circuits and providing the delayed values at later times to other compositor circuits downstream, a finalization circuit, and a control circuit operating counters and producing control signals coupled to the compositors, the delay circuits, and the finalization circuit.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: June 7, 2022
    Assignee: Gigantor Technologies, Inc.
    Inventor: Mark Ashley Mathews
  • Patent number: 11354129
    Abstract: A system for predicting latency of at least one variable-latency instruction, wherein a microprocessor includes at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor is configured to issue at least one dependent instruction, execute the at least one pipeline to serve at least one variable-latency instruction, generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 7, 2022
    Inventor: Jeremy L. Branscome
  • Patent number: 11354132
    Abstract: A method and a system are presented for load balancing of two processors when executing diverse-redundant instruction sequences.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 7, 2022
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Thomas Huehn
  • Patent number: 11347504
    Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 31, 2022
    Assignee: Korea Electronics Technology Institute
    Inventors: Byung Soo Kim, Young Jong Jang, Young Kyu Kim
  • Patent number: 11347505
    Abstract: A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 31, 2022
    Assignee: International Business Machines Corporation
    Inventors: Shakti Kapoor, Karen E. Yokum, John A. Schumann
  • Patent number: 11340960
    Abstract: Systems, methods, and apparatuses relating to circuitry to implement lockstep of processor cores are described. In one embodiment, a hardware processor comprises a first processor core comprising a first control flow signature register and a first execution circuit, a second processor core comprising a second control flow signature register and a second execution circuit, and at least one signature circuit to perform a first state history compression operation on a first instruction that executes on the first execution circuit of the first processor core to produce a first result, store the first result in the first control flow signature register, perform a second state history compression operation on a second instruction that executes on the second execution circuit of the second processor core to produce a second result, and store the second result in the second control flow signature register.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Umberto Santoni, Philip Abraham
  • Patent number: 11340903
    Abstract: The present application discloses a processing method, device, equipment and storage medium of a loop instruction, and relates to the fields of voice and chips. A specific embodiment is: acquiring a computer program including a first loop body, where the first loop body is generated according to a second loop body in a software code to be compiled, the first loop body includes a plurality of first loop instructions, the plurality of first loop instructions can be identified by a hardware structure of a computer device; in the case that the first loop body is detected, determining loop parameters of the first loop body according to the plurality of first loop instructions; acquiring the plurality of first loop instructions according to the loop parameters of the first loop body; executing the plurality of first loop instructions.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 24, 2022
    Inventors: Junhui Wen, Chao Tian
  • Patent number: 11321097
    Abstract: The disclosed inventions include a processor apparatus and method that enable a general purpose processor to achieve twice the operating frequency of typical processor implementations with a modest increase in area and a modest increase in energy per operation. The invention relies upon exploiting multiple independent streams of execution. Low area and low energy memory arrays used for register files operate a modest frequency. Instructions can be issued at a rate higher than this frequency by including logic that guarantees the spacing between instructions from the same thread are spaced wider than the time to access the register file. The result of the invention is the ability to overlap long latency structures, which allows using lower energy structures, thereby reducing energy per operation.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 3, 2022
    Assignee: Intensivate Inc.
    Inventor: Kevin Sean Halle
  • Patent number: 11321086
    Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Dipankar Das, Naveen K. Mellempudi, Mrinmay Dutta, Arun Kumar, Dheevatsa Mudigere, Abhisek Kundu
  • Patent number: 11314506
    Abstract: Provided is a secure computation device for computing a comparison operation to two integers without the use of AND/XOR. The secure computation device compares a first integer a and a second integer b when the first integer a and the second integer b, which are 0 or greater and less than 2{circumflex over (?)}k (k being an integer of 1 or greater), are subjected to ring sharing. The secure computation device includes: an addition/subtraction circuitry; a bit decomposition circuitry; and a bit extraction circuitry. The addition/subtraction circuitry uses the first integer a, the second integer b, and 2{circumflex over (?)}k to carry out a predetermined addition or subtraction with ring sharing, and output an added/subtracted result. The bit decomposition circuitry converts the added/subtracted result to bit sharing, and outputs a bit shared result. The bit extraction circuitry extracts a (k+1)-th bit of the bit shared result, and outputs an extracted result.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 26, 2022
    Inventor: Kazuhisa Ishizaka
  • Patent number: 11314513
    Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 26, 2022
    Inventors: Gregory Trunde, Denis Dutey
  • Patent number: 11294672
    Abstract: Techniques are disclosed relating to routing circuitry configured to perform permute operations for operands of threads in a single-instruction multiple-data group. In some embodiments, an apparatus includes hierarchical operand routing circuitry configured to route operands between a set of single-instruction multiple-data (SIMD) pipelines based on a permute instruction. In some embodiments, the routing circuitry includes a first level and a second level. The first level may include a set of multiple crossbar circuits each configured to receive operands from a respective subset of the pipelines and output one or more of the received operands on multiple output lines based on the permute instruction, where the crossbar circuits support full permutation within a respective subset.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 5, 2022
    Assignee: Apple Inc.
    Inventors: Robert D. Kenney, Liang-Kai Wang, Terence M. Potter
  • Patent number: 11288074
    Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array.
    Type: Grant
    Filed: March 31, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 11281470
    Abstract: A processing device is provided which comprises memory and a processor. The processor is configured to receive an array of floating point numbers each having a plurality of bits used to represent a probability value. For each floating point number, the processor is configured to replace values in a portion of the bits used to represent the probability value with index values to represent an index corresponding to a location of a corresponding floating point number in the memory. The processor is also configured to process the floating point numbers using SIMD instructions to execute one of an argmax operation and an argmin operation.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 22, 2022
    Inventors: Michael L. Schmit, Lakshmi Kumar