Abstract: An apparatus comprises processing circuitry comprising a plurality of execution units; issue circuitry to issue an instruction to be executed by the processing circuitry during a plurality of pipeline stages such that younger instructions are not permitted to be issued before older instructions and scheduling circuitry to schedule instructions for execution in a given cycle during the plurality of pipeline stages, such that the instruction is permitted to be executed in an order different to a program order in response to input operand data being available, by dynamically allocating which of the plurality of pipeline stages a given execution unit of the plurality of execution units is assigned to in the given cycle. In a configuration selectable for the given cycle, the scheduling circuitry causes the given execution unit of the plurality of execution units to be assigned to any pipeline stage of the plurality of pipeline stages.

Abstract: Systems and methods for efficient selection of single instruction multiple data operations for neural processing units. An example processor system comprises a matrix processor configured to perform convolutions associated with a neural network and single instruction multiple data (SIMD) processors in communication with the matrix processors, with the SIMD processors being configured to execute a group of operations based on a current position associated with processing the neural network, and with the group of operations being selected from multiple SIMD programs, and with the group of operations being selected from the SIMD programs according to the current position.

Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. In response to a command to operate the IC with multiple cores, the first pipeline is flushed. The first core is partitioned to obtain a second core and a third core. The first pipeline is partitioned to obtain a second pipeline and a third pipeline. The first set of hardware structures is partitioned to obtain a second set of hardware structures and a third set of hardware structures. The first thread is executed on the second pipeline of the second core of the IC, the second core including the second set of hardware structures. A second thread is executed on the third pipeline of the third core of the IC, the third core including the third set of hardware structures.

Abstract: There is provided an apparatus, a method, a chip containing product, a system and a medium. The apparatus is provided with an instruction fetch queue for storage of instruction fetch entries, and prefetching circuitry configured, for each instruction fetch entry and in response to a determination that a block of instructions indicated by that instruction fetch entry is not present in instruction storage circuitry, to issue a request to fetch the block and to cause the block to be allocated to the instruction storage circuitry. The apparatus is also provided with control circuitry configured to suppress issuing the request in response to a number of outstanding requests meeting or exceeding a variable throttling threshold. The control circuitry is configured to derive the variable throttling threshold from properties of previously fetched blocks, the properties determined before or during storage of the previously fetched blocks in the instruction storage circuitry.

Abstract: An apparatus and method for efficiently scheduling instructions for a parallel data processing circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple compute circuits, each uses multiple single instruction multiple data (SIMD) circuits. Each compute circuit includes a scheduler for selecting instructions to issue to the SIMD circuits. During execution, a thread executes an instruction that provides a point of synchronization. Examples are the wait instruction and the barrier instruction. A control circuit accesses the metrics indicating hardware behavior of the corresponding wave. Based on these metrics, the control circuit generates a prediction of the amount of time before the point of synchronization completes. For example, the prediction indicates how soon each of the other threads of the corresponding wave are to arrive at the point of synchronization. The prediction is used to update control flow of the thread.

Abstract: An apparatus comprises exception return state register storage, and processing circuitry. In response to a guarded control stack (GCS) exception return state push instruction, the processing circuitry obtains exception return state information from the exception return state register storage and push the state information to a GCS data structure. In response to a GCS exception return state pop instruction, the processing circuitry obtains GCS-protected exception return state information from the GCS data structure. In at least one operating state, the processing circuitry detects, in response to an attempt to modify the exception return state information stored in the exception return state register storage, whether an exception return state lock parameter is in a locked state or an unlocked state, and signals a fault when it is in the locked state.

Abstract: Branch target buffer structures are provided. A device can include a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers that have progressively slower access times. The device can include a first program counter configured to generate a first program counter value associated with a next instruction of an executing application. The device can include a second program counter configured to predict a second program counter value that is associated with a subsequent instruction of the executing application that is after the next instruction. The device can include first branch prediction circuitry configured to populate a branch target buffer of the branch target buffers based on the second program counter value.

Abstract: Apparatuses, computer programs and methods are disclosed, relating 2D arrays of data elements and a 2D array of processing elements. A first 2D array of data elements provides data values for processing by each processing element and a second 2D array of data elements provides control values controlling the processing. The 2D array of processing elements has a data flow direction across the 2D array of processing elements, and the data flow direction proceeds from a starting set of processing elements of the 2D array of processing elements. For each processing element not in the starting set of processing elements, the data processing operation preformed takes as an operand a respective data value provided by a neighbouring data element of the first 2D array of data elements and selection of the neighbouring processing element is controlled by a corresponding source control value in the second 2D array of data elements.

Abstract: Apparatuses, systems, and techniques to perform a matrix multiply-accumulate (MMA) instruction to exclusively store information to be used by the MMA instruction. In at least one embodiment, a processor retrieves matrix information from a memory that exclusively stores and performs a multiplication computation using said matrix information.

Abstract: An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.

Abstract: A processing system includes one or more network-attached hostless accelerator (NAHA) units each having an integrated circuit. The integrated circuit of each NAHA unit includes a memory and a first network interface controller configured to communicatively couple the memory to a network such that the memory of the NAHA unit is communicatively coupled to one or more memories of other NAHA units via the network. Additionally, a NAHA unit of the processing system includes one or more processor cores configured to execute an instruction to generate a result. Further, the one or more processor cores of the NAHA unit are configured to store the result in the one or more memories of the other NAHA units.

Abstract: In various examples, systems and methods are disclosed that relate to programming multi-dimensional single instruction, multiple data (SIMD) processors (also referred to as an accelerator). In one example, a processor can obtain instructions to be performed by the accelerator. The processor can determine one or more operations to be performed by the accelerator based at least on the instructions and generate a set of accelerator instructions. In examples, the processor can then provide data associated with the accelerator instructions to cause the accelerator to perform at least a portion of the one or more operations.

Abstract: Segment load operations are performed by processing data through an anything-to-anything mux, and sections writing elements to respective storage locations based on corresponding indices of the elements and the storage locations. Once all of the elements are loaded into the correct storage location, each location is read again with the elements of that storage location being sent through the mux, arranged) into the correct order, and written back to the same register.

Abstract: Disclosed are techniques for runtime adaptive prefetching in a many-core system. In an aspect, a method for runtime adaptive prefetching in a many-core system may include periodically performing the following steps: determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core; determining a first prefetching configuration from a plurality of prefetching configurations based on the workload classification; and configuring at least the first processor core according to the first prefetching configuration.

Abstract: Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand.

Abstract: Techniques are disclosed involving selection circuitry for stored operands. An embodiment of an apparatus includes a random-access storage element array and a permute network. The storage element array is configured to store a set of input data to an operation in a set of entries allocated among one or more execution lanes. The permute network is connected to each entry of the set of entries and is configured to select from among the set of entries to provide operands to one or more source inputs of execution circuitry configured to perform the operation. For a given source input, the permute network provides connection to only a subset of the entries that are allocated to a given execution lane. In a further embodiment, the permute network is configured to support multiple modes of the operation.

Abstract: Disclosed is a method for resetting configurable units in a reconfigurable processor with an array of configurable units and a force-quit controller on an integrated circuit substrate. The array includes multiple sub-arrays of configurable units. The method involves receiving a force-quit command at the force-quit controller and generating force-quit control signals to reset configurable units in a specific sub-array of the plurality of sub-arrays. The specific sub-array contains the force-quit controller. This method enhances the efficiency and reliability of reconfigurable processors by enabling targeted and controlled resets of configurable units within the reconfigurable processor architecture.

Abstract: A hardware accelerator is disclosed that can flexibly be configured to support differing data types and differing operation flows. The hardware accelerator includes a plurality of fixed tensor operation logic units, tensor operation pipeline logic configured to receive from the processor a pipeline command including a software-defined tensor operation pipeline definition defining a plurality of tensor operation stages in a tensor operation pipeline and associated predetermined tensor operations to be performed at each of the defined tensor operation stages. The hardware accelerator is further configured to receive tensor data to be computed by the tensor operation pipeline, and implement the tensor operation pipeline to perform the tensor operations in each of the tensor operation stages on the tensor data, to thereby produce a tensor operation pipeline result for the tensor data, and output the tensor operation pipeline result to the processor.

Abstract: At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.

Abstract: Systems, methods, and apparatuses for implementing capability informed prefetches are described.