Patents Examined by Corey S Faherty
  • Controlling timing in computer processing
    Patent number: 11416440
    Abstract: A computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising: a switch control instruction which when executed causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in the sequence of instructions and its execution by the execution unit.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 16, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Richard Luke Southwell Osborne, Alan Graham Alexander, Stephen Felix
  • Program instruction fusion
    Patent number: 11416252
    Abstract: A data processing system includes an instruction pipeline containing instruction queue circuitry, fusion circuitry and decoder circuitry. The fusion circuitry serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry which decodes X program instructions in parallel using parallel decoders.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 16, 2022
    Assignee: Arm Limited
    Inventors: Vladimir Vasekin, Chiloda Ashan Senarath Pathirane, Jungsoo Kim, Alexei Fedorov
  • RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method thereof
    Patent number: 11409529
    Abstract: The present invention relates to a hardware high-speed computation combined RISC-V based computation device for supporting a user-defined instruction set and a method thereof which configures a hardware high-speed computation unit executing a user-defined function through a field programmable gate array (FPGA) in a single chip together with a RISC-V based computation device, executes general computation and user-defined computation in an instruction level, not a separate bus connection configuration, through a program using a RISC-V based instruction set including a user-defined instruction set, and provides flexibility capable of optionally changing the user-defined instruction set and a corresponding function and a method thereof.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 9, 2022
    Assignee: ZARAM TECHNOLOGY CO., LTD.
    Inventors: Tae Jong Lee, Sung Hoon Park, In Shik Seo, Joon Hyun Baek
  • Selecting instructions for a value predictor
    Patent number: 11409532
    Abstract: Apparatuses and methods of data processing are disclosed for processing circuitry having a pipeline of multiple stages. Value prediction storage circuitry holds value predictions, each associated with an instruction identifier. The value prediction storage circuitry performs look-ups and provides the processing circuitry with data value predictions. The processing circuitry speculatively issues a subsequent instruction into the pipeline by provisionally assuming that execution of a primary instruction will result in the generated data value prediction. Allocation of entries into the value prediction storage circuitry is based on a dynamic allocation policy, whereby likelihood of allocation into the value prediction storage circuitry of an data value prediction increases for an executed instruction when the executed instruction is associated with at least one empty processing stage in the pipeline.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: August 9, 2022
    Assignee: Arm Limited
    Inventors: Vladimir Vasekin, David Michael Bull, Sanghyun Park, Alexei Fedorov
  • Processor including debug unit and debug system
    Patent number: 11409636
    Abstract: The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 9, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Taotao Zhu, Chen Chen
  • Processor having multiple operating modes
    Patent number: 11409531
    Abstract: Disclosed is a processor having multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 9, 2022
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Chen Chen, Taotao Zhu, Chang Liu
  • Introducing noise in threaded execution to mitigate cross-thread monitoring
    Patent number: 11403101
    Abstract: Described herein are systems and methods for introducing noise in threaded execution to mitigate cross-thread monitoring. For example, some systems include an integrated circuit including a processor pipeline that is configured to execute instructions using an architectural state of a processor core; data storage circuitry configured to store a thread identifier; and a random parameter generator. The integrated circuit may be configured to: determine a time for insertion based on a random parameter generated using the random parameter generator; at the time for insertion, insert one or more instructions in the processor pipeline by participating in thread arbitration using the thread identifier; and execute the one or more instructions using one or more execution units of the processor pipeline.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 2, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Rabin Sugumar
  • Control flow barrier and reconfigurable data processor
    Patent number: 11386038
    Abstract: A reconfigurable data processor comprises an array of processing units arranged to perform execution fragments of a data processing operation. A control barrier network is coupled to processing units in the array. The control barrier network comprises a control bus configurable to form signal routes in the control barrier network, and a plurality of control barrier logic units having inputs and outputs connected to the control bus and to the array of processing units. The logic units in the plurality of logic units are configurable to consume source tokens and status signals on the inputs and produce barrier tokens on the outputs based on the source tokens and status signals on the inputs. Also, the logic units can produce enable signals for the array of processing units based on the source tokens and status signals on the inputs.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 12, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Manish K. Shah, Ram Sivaramakrishnan, Pramod Nataraja, David Brian Jackson, Gregory Frederick Grohoski
  • Branch prediction cache for multiple software workloads
    Patent number: 11385899
    Abstract: An apparatus comprises: processing circuitry 18 to process instructions from a plurality of software workloads; a branch prediction cache 40-42 to cache branch prediction state data selected from a plurality of sets of branch prediction state data 60 stored in a memory system 30, 32, 34, each set of branch prediction state data corresponding to one of said plurality of software workloads; and branch prediction circuitry 4 to predict an outcome of a branch instruction of a given software workload based on branch prediction state data cached in the branch prediction cache from the set of branch prediction state data corresponding to said given software workload. This is useful for mitigating against speculation side-channel attacks which exploit branch mispredictions caused by malicious training of a branch predictor.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 12, 2022
    Assignee: Arm Limited
    Inventor: Alastair David Reid
  • Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learning
    Patent number: 11379708
    Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), includes a dynamic power controller for adjusting operating voltage and/or frequency. The controller may receive current power used by the integrated circuit and a predicted power determined based on instructions pending in a plurality of processors. The controller determines adjustments that need to be made to the operating voltage and/or frequency to minimize the difference between the current power and the predicted power. An in-system reinforced learning mechanism is included to self-tune parameters of the controller.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 5, 2022
    Assignee: NVIDIA Corporation
    Inventors: Sachin Idgunji, Ming Y. Siu, Alex Gu, James Reilley, Manan Patel, Rajeshwaran Selvanesan, Ewa Kubalska
  • Microprocessor with multistep-ahead branch predictor
    Patent number: 11379243
    Abstract: A microprocessor with a multistep-ahead branch predictor is shown. The branch predictor is coupled to an instruction cache and has an N-stage pipelined architecture, which is configured to perform branch prediction to control the instruction fetching of the instruction cache. The branch predictor performs branch prediction for (N?1) instruction-address blocks in parallel, wherein the (N?1) instruction-address blocks include a starting instruction-address block and (N?2) subsequent instruction-address blocks. The branch predictor is thereby ahead of branch prediction of the starting instruction-address block. The branch predictor stores reference information about branch prediction in at least one memory and performs a parallel search of the memory for the branch prediction of the (N-1) instruction-address blocks.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 5, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Fangong Gong, Mengchen Yang, Guohua Chen
  • Detection method of control flow attacks based on return address signatures
    Patent number: 11372967
    Abstract: A control flow attacks based on return address signatures comprises: using a return address as a push return address when a response is given to an interrupt service routine; generating an encrypted push return address by an XOR encryption circuit by means of an n-bit binary key generated by a pseudo random number generator; then, generating a push_address signature value by an MD algorithm signature circuit; when the response to the interrupt service routine is over, reading an n-bit binary address out of a stack to serve as a pop return address; generating an encrypted pop return address by the XOR encryption circuit; generating a pop address signature value by the MD algorithm signature circuit; comparing the push_address signature value with the pop address signature value; and determining whether or not a data processor is under a control flow attack according to a comparison result.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Wenzhou University
    Inventors: Pengjun Wang, Yunfei Yu, Jiana Lian, Gang Li, Bo Chen, Yuejun Zhang
  • Completion mechanism for a microprocessor instruction completion table
    Patent number: 11366671
    Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 21, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak K. Singh
  • Microprocessor with high-efficiency decoding of complex instructions
    Patent number: 11366665
    Abstract: Microcode combination of complex instructions is shown. A microprocessor includes an instruction queue, an instruction decoder, and a microcode controller. The instruction decoder is coupled to the instruction queue. The microcode controller is coupled to the instruction decoder and has a memory. The memory stores a combined microcode for M complex instructions arranged in a specific order, where M is an integer greater than 1. When the M complex instructions in the specific order have popped out of the first to M-th entries of the instruction queue, the instruction decoder operates the microcode controller to read the memory for the combined microcode with microcode reading trapping happened just once.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 21, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventor: Yingbing Guan
  • Instruction sequence merging and splitting for optimized accelerator implementation
    Patent number: 11360772
    Abstract: Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 14, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alper Buyuktosunoglu, David Trilla Rodriguez, John-David Wellman, Pradip Bose
  • Instructions and logic to perform floating point and integer operations for machine learning
    Patent number: 11360767
    Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Slice-based allocation history buffer
    Patent number: 11360775
    Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Gregory W. Alexander, Dung Q. Nguyen
  • Parallel implementation of deep neural networks applied to three-dimensional data sets
    Patent number: 11354571
    Abstract: An integrated circuit (IC) implements an L by M by N three-dimensional aperture function throughout a P by R by C three-dimensional source array. The IC has an input port receiving an ordered stream of independent input values from the source array, an output port producing an ordered stream of independent output values, an array of n compositor circuits, where n=L×M×N, each compositor circuit implementing a sub-function of the aperture function, dedicated pathways between the compositor circuits, delay circuits on the IC receiving values on the dedicated pathways from individual ones of the compositor circuits and providing the delayed values at later times to other compositor circuits downstream, a finalization circuit, and a control circuit operating counters and producing control signals coupled to the compositors, the delay circuits, and the finalization circuit.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: June 7, 2022
    Assignee: Gigantor Technologies, Inc.
    Inventor: Mark Ashley Mathews
  • System and method for predicting latency of a variable-latency instruction
    Patent number: 11354129
    Abstract: A system for predicting latency of at least one variable-latency instruction, wherein a microprocessor includes at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor is configured to issue at least one dependent instruction, execute the at least one pipeline to serve at least one variable-latency instruction, generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 7, 2022
    Assignee: SPREADTRUM HONG KONG LIMITED
    Inventor: Jeremy L. Branscome
  • Load balancing of two processors when executing diverse-redundant instruction sequences
    Patent number: 11354132
    Abstract: A method and a system are presented for load balancing of two processors when executing diverse-redundant instruction sequences.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 7, 2022
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Thomas Huehn