Patents Examined by Courtnay A. Bowers
  • Patent number: 5306923
    Abstract: An optoelectronic device with a very low series resistance has a III-V substrate, a lower, n-doped III-V material semiconducting confinement layer placed on the substrate, an active zone having at least one active, not intentionally doped III-V material semiconducting layer placed on the lower confinement layer, an upper, p-doped III-V material semiconducting confinement layer covering said active zone, the forbidden energy band of the active layer being lower than that of the confinement layers. Two metal coatings are placed on two opposite faces of the device and there is a highly n-doped, quaternary III-V material semiconducting layer for stopping the diffusion of doping ions from the upper confinement layer and placed between the active layer and the upper confinement layer, said stopping layer having a thickness smaller than that of the active layer and also forming part of the active zone.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: April 26, 1994
    Assignee: France Telecom
    Inventors: Christophe Kazmierski, Benoit Rose
  • Patent number: 5298785
    Abstract: A multi-emitter type semiconductor device having multiple transistors coupled in parallel which utilize a common substrate. Between a selected emitter electrode and a base contact, a stabilizing resistive region is formed in the common substrate. In order to reduce the parasitic effects due to this region an additional emitter ballast resistor may be formed on the surface of an insulating layer over the substrate. This supplemental resistor formed on the insulating layer is made from polycrystalline silicon. Alternatively, the supplemental resistor can be combined with the resistance of the stabilizing region in a single resistor located on the surface of the insulating layer.
    Type: Grant
    Filed: April 18, 1991
    Date of Patent: March 29, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Ito, Jiro Terashima
  • Patent number: 5049970
    Abstract: A high resistive element is provided that constitutes an element of integrated circuits comprising an oxide film formed on a semiconductor substrate and a polysilicon film formed on the oxide film. The high resistive element is prepared by ion injection of silicon ions and conductive impurities in the oxide film through the polysilicon film.
    Type: Grant
    Filed: June 12, 1990
    Date of Patent: September 17, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Tanaka, Shigeo Onishi, Toshiyuki Okumura, Keizo Sakiyama