Abstract: A computer comprising a processor, a volatile main store, a non-volatile random access memory (NVRAM) mirror store, and optionally a cache for the non-volatile mirror store. While programs of the computer are operational, the contents of the volatile main store are mirrored in the non-volatile mirror store such that when a startup signal is received, the contents of the volatile main store are quickly restored from the contents of the non-volatile mirror store.

Abstract: A method and system for determining the memory utilization of a heap are provided. With the method and system, object allocations and optionally, possible memory freeing events are used to initiate a mark-and-count operation. The mark-and-count operation marks the live objects and maintains a running count of their memory bytes allocated to the live objects, referred to as a live count. The execution of the mark-and-count operation may be dependent upon various criteria including thresholds, functions of the live count, peak live counts, number of memory bytes allocated since a previous mark-and-count operation was performed, and the like. In addition to the live count, a total number of bytes allocated to objects may be maintained in order to obtain information regarding the heap memory utilization.

Abstract: A buffer random access memory has a first portion reserved for a defect table and a second portion reserved for data caching. A method of managing the buffer random access memory includes determining actual memory space of the first portion which is occupied by the defect table. This identifies unused memory space of the first portion of the buffer random access memory. The method then includes reallocating the unused memory space of the first portion of the buffer random access memory for use in data caching. Controllers and mass storage devices which implement the method are also provided.

Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices are combined. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group the volumes belonging to the storage system, as a plurality of storage layers 1-3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes to be moved V1 and V2, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.

Abstract: A data processing system includes a first storage system including a first host and a first storage subsystem. The first host has access to a first copy manager that is operable to manage a data replication operation. A second storage system includes a second host and a second storage subsystem. The second host has access to a second copy manager that is operable to manage a data replication operation. A first communication link is coupled to the first storage system and the second storage system to exchange management information between the first and second storage systems in order to manage the data replication operation. A data transfer path is configured to transfer data stored in the first storage subsystem to the second storage subsystem and replicate the data of the first storage subsystem in the second storage subsystem. The data transfer path is different from the first communication link.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: A method for managing incremental storage includes a storage pool management module that allocates storage volumes to a virtual volume. Also included is an incremental log corresponding to the virtual volume, which maps virtual addresses to storage addresses. The method may also include a replication module that sends replicated data to the virtual volume and a policy management module that determines allocation criteria for the storage pool management module. In one embodiment, the incremental log includes a look up table that translates read and write requests to physical addresses on storage volumes within the virtual volume. The replicated data may include incremental snapshot data corresponding to one or more primary volumes. The various embodiments of the virtual incremental storage method facilitate dynamic adjustment of the storage capacity of the virtual volume to accommodate changing amounts of storage utilization.

Abstract: A method and apparatus wherein only a partial key is stored in a hashing table is disclosed. By storing a partial key as opposed to storing the entire original key, less data is required to be stored in the hash table. This reduces the attendant memory costs. The reduction in memory requirement does not degrade the hash functionalities whatsoever. Hashing conflicts can be fully resolved by consulting the partial key.

Abstract: Methods and apparatus are provided for managing data in a hierarchal storage subsystem. A plurality of volumes is designated as a storage group for Level 0 storage; a threshold is established for the storage group; space is allocated for a data set to a volume of the storage group; the data set is stored to the volume; the threshold is compared with a total amount of space consumed by all data sets stored to volumes in the storage group. Data sets are migrated from the storage group to a Level 1 storage if the threshold is less than or equal to the total amount of space used by all of the data sets stored to volumes in the storage group. Thus, contention between migration and space allocation is reduced.

Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices coexist. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group arbitrarily each volume belonging to the storage system, as a plurality of storage layers 1-3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes V1 and V2 to be moved, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.

Abstract: A method detects a programmable pattern (e.g., Ethernet comma or SONET A1A2 frame) and simultaneously byte aligns to that pattern. The technique uses a content addressable memory (CAM) programmed (e.g., selected by the user) with a particular pattern to enable detecting of a symbol or symbols, or pattern, of bits in an incoming serial stream. The circuitry deserializes the serial stream and byte aligns parallel data based on output from the CAM and a state machine.

Abstract: In an exclusive lock management in common to both the In-Band and the Out-of-band, a lock control technique of a storage system capable of removing the factor that may cause the discrepancy in the configuration information in a disk array system is disclosed. In the storage system, a shared memory in a DKC of a storage subsystem has lock management information for uniformly managing the operation authority for the configuration information in the shared memory that is used in common by both the channels of the host terminals and the management client terminals, and a CPU in the DKC gives the operation authority for changing the configuration information to either the host machine or the management client based on the lock management information in the shared memory in response to an access request from the host terminals or the management client terminals.

Abstract: A memory device includes a cell area having N+1 unit cell blocks. Each cell block includes M word lines. The N unit cell blocks are each corresponded to a logical cell block address. The one additional unit cell block is added for accessing data with high speed. A tag block receives a row address, senses the logical cell block address in the row address and outputs a physical cell block address based on the logical cell block address and the candidate information. The tag block includes:N+1 unit tag tables corresponding to the N+l unit cell blocks. Each tag block has M number of registers. The M number of registers correspond to M number of word lines of the corresponding unit cell blocks. Each register stores one logical cell block address. The tag block also includes an initialization unit that initializes the N+1 unit tag tables.

Abstract: Buffer memories having hardware controlled buffer space regions in which the hardware controls the dimensions of the various buffer space regions to meet the demands of a particular system. The hardware monitors the usage of the buffer data regions over time and subsequently and automatically adjusts the dimensions of the buffer space regions based on the utilization of those buffer regions.

Abstract: An apparatus and method for a storage system for storing data on an object basis, where the object has attribute information and data. The storage system has a plurality of (N) data storage devices and at least one redundant data storage device. When the storage system receives a write request with an object, the object is divided into N sub-objects each of which have the same size. Thereafter, each of the N sub-objects is written to the data storage devices. Further, the parity is calculated from each of the sub-objects. In one embodiment the parity is stored in a redundant data storage device.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A method and system to detect an occurrence of a predetermined event within the system, and change a power state of a hard drive (HD) in response to the event, are described. In one embodiment, in response to detecting consecutive HD reads have been satisfied by a non-volatile cache (NVC) of the HD, for at least a predetermined period of time, or detecting that a predetermined quantity of consecutive HD reads have been satisfied by the NVC, spinning down the HD. In an alternative embodiment, in response to detecting a predetermined number of HD data transactions have been serviced by the NVC or the HD, canceling a planned spinning down of the HD or spinning up the HD.

Abstract: A method of dynamically allocating a variable in a tracing framework, including allocating a dynamic memory in the tracing framework having a plurality of data chunks, placing at least one of the plurality of data chunks onto a free list, allocating the at least one of the plurality of data chunks on the free list to store the variable and removing the at least one of the plurality of data chunks from the free list, deallocating the at least one of the plurality of data chunks and placing the at least one of the plurality of data chunks on a dirty list, and cleaning the at least one of the plurality of data chunks on the dirty list using a cleaning procedure to place the one of the plurality of data chunks on the free list.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.