Patents Examined by Craig Evan Walter
  • Patent number: 7024535
    Abstract: The invention concerns a method for dynamically allocating memory workspace of an onboard system to a data structure identified by an identification number (ID_Ak) and the corresponding onboard system. The storage area of the onboard system being subdivided into elementary memory blocks (BL1), the method is implemented on the basis of an allocation instruction and an erasure instruction. To allocate (A) an elementary memory block, the method consists in assigning an identification number (ID-Ak) to the block concerned. To erase (E) an elementary storage block, the method consists in assigning an arbitrary value (AAAA) different from any identification number. The system is applicable to onboard systems, such as multi-application microprocessor cards.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: April 4, 2006
    Assignee: CP8 Technologies
    Inventors: Nicolas Fougeroux, Patrice Hameau, Olivier Landier
  • Patent number: 7010659
    Abstract: A method for setting up a disk-array device, which includes at least one connection port for connection with at least one computer and at least one storage volume for storing data, comprises the steps of: loading configuration-defining data to an information processing device that is connected to the disk-array device, the configuration-defining data being in an electronic-data form; the information processing device generating, in accordance with the configuration-defining data, a setup command for setup of the disk-array device and transmitting the setup command to the disk-array device; and the disk-array device receiving the setup command and performing the setup according to the setup command.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Takeuchi, Yasufumi Uchiyama, Shotaro Ohno, Daisuke Shinohara
  • Patent number: 6993627
    Abstract: A data storage system (100) and a method of storing data are described including a cache (118) with a variable number of levels (210, 220, 230, 240). Each level in the cache (118) has a cache controller (212, 222, 232, 242) and a cache memory (214, 224, 234, 244) for storing data. An address mapping is recorded and applied between each of the levels of the cache (118). The address mapping corresponds to a point in time virtual copy operation such as a snapshot copy operation applied to the cache (118) and enables point in time virtual copy operations to be carried out in electronic time. A new level is created in the cache (118) when a point in time virtual copy operation is received by the cache and a corresponding address mapping is applied to the previous level in the cache (118).
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Robert Bruce Nicholson