Abstract: A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity.

Abstract: A method for opening resist in raised areas of a semiconductor device. In one aspect, a conductive layer is formed over a channel insulator layer to form a raised portion including a height above a substantially planar surrounding area, the channel insulator layer being aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area, and patterned by employing a gray scale light mask to reduce exposure light on the photoresist over the raised portion. Then, the photoresist is etched to thin it such that a gap is formed in the photoresist down to the conductive layer over the raised portion, but the photoresist remains everywhere else, and the conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.

Abstract: A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid phase doping to form extension regions. Generally, a doped material is provided adjacent to a transistor gate structure and the IC is annealed. During the annealing process, dopants from the doped material diffuse into the semiconductor substrate to form the source and drain extension regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).