Abstract: The present invention includes a method of eliminating interference from an undersettled electrical signal, the undersettled electrical signal including a test signal at a known frequency. One embodiment of the present invention includes a method comprising the steps of providing a digitized version of the undersettled electrical signal (at 46); generating a frequency spectrum of the digitized version of the undersettled electrical signal (at 56); spectrally interpolating the frequency spectrum to generate an interference signal frequency spectrum (at 65); and subtracting the interference signal frequency spectrum (at 65) from the undersettled signal frequency spectrum (at 56) generating a settled signal spectrum (at 75).

Abstract: A coding system for data compression and decompression of a digitized source signal, for example in accordance with the MPEG audio standard, includes an analysis filter in which an inverse discrete cosine transform operation is employed during data encoding, and a synthesis filter in which a discrete cosine transform is performed during data decoding.

Abstract: A notification system for reporting events occurring within a defined area being monitored thereby. The notification system includes a plurality of sensors installed at selected locations within the defined area and a sensor interface coupled to each of the sensors. The sensor interface periodically polls the sensors and stores status information received therefrom. Coupled to the sensor interface is a computer system for receiving and analyzing the stored status data. Upon determining from the status data that an event requiring issuance of a notification has occurred, the computer system issues a series of notifications for which each recipient of a notification receives a selected message regarding the event.

Abstract: Specific noise components in an input signal are identified and isolated for processing in a desired manner. The method comprises determining an interval during which the noise component is expected to occur and isolating a portion of the input signal occurring during that interval. Determination of the interval is made by sensing noise impulses in the input signal, temporally correlating the noise impulses, and estimating the time that the noise impulses are expected to recur. The input signal can then be passed during the interval to an output signal to enhance the noise component, or the input signal can be blanked from the output signal to reduce the noise component.

Abstract: A motion vector detecting circuit is for detecting a motion vector in moving picture coding using motion compensation prediction in the unit of block composed of L pixels by block matching between a block in a prediction target image and a candidate block in a reference image. The motion vector detecting circuit comprises a calculating section for calculating a first prediction error between a block in a prediction target image and a candidate block in a reference image using L1 (<L) pixels in block, comparing the first prediction error thus calculated with a threshold, and calculating a second prediction error between a block in the prediction target image and a candidate block in the reference image using L2 (L1<L2.ltoreq.

Abstract: The present invention relates to a method and process for manufacturing an improved machine tool collet. The invention further relates to an improved machine tool collet having design parameters optimized to maximize the gripping strength of the collet. The collet according to the invention is of the type having a plurality of gripping jaws spaced around a common longitudinal axis with resilient material between the gripping jaws. The method includes calculating the total torque generated on a bar passing through the collet for a given collet configuration having predetermined design parameters. The total torque includes the torque generated just prior to a toggle condition occurring between the gripping jaws and the bar and the maximum moment force generated between the gripping jaws and the bar at a toggle condition.

Abstract: A dynamical system analyzer (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are loaded into a finite impulse response filter (34). The time series is formed into Takens' vectors each of which is projected onto each of the singular vectors by the filter (34). Each Takens' vector thereby provides the co-ordinates of a respective point on a trajectory of the system (14) in a phase space. A heuristic processor (44) is used to transform delayed co-ordinates by QR decomposition and least squares fitting so that they are fitted to non-delayed co-ordinates. The heuristic processor (44) generates a mathematical model to implement this transformation, which predicts future system states on the basis of respective current states. A trial system is employed to generate like co-ordinates for transforation in the heuristic processor (44).

Abstract: Circular reference features such as drilled holes are located in an area of a part such as a cylinder head, the surface of which is laser scanned to obtain scan data. The scan data provides height values of the part. Differences in height values are used to determine the points on scan lines which are boundary points of the circular holes. A first algorithm is used to estimate the contour and radius of each hole. A second algorithm provides a correction factor for the radius of each hole. The circular reference features are used for registering the part relative to a reference datum. Methods are provided that allow the accurate determination of the location of such reference features to within 0.01 mm. (0.0004 in.) from the scan data. The method may be utilized to create modified scan data to machine the part. The method may be utilized iteratively from different views of the part to obtain data which represents the part.

Abstract: Hotelling's T.sup.2 statistical analysis and control is used to provide multivariate analysis of components of an RF spectra for real time, in-situ control of an ongoing semiconductor process. An algorithm calculates the T.sup.2 value which is then used to generate a feedback signal, if the T.sup.2 value is out of range, to indicate an out-of-tolerance condition.

Abstract: A system for anti-lock brake and traction control has a control circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, and wheel speed determination from the square waves. The state machine algorithm tracks signal peaks and valleys and uses a dual hysteresis method of generating output transitions to capture all cycles of a signal having single cycle anomalies while rejecting noise. A single rear wheel sensor having twice the frequency of front wheel sensors for equal wheel speeds is processed twice as often as each front sensor. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits.

Abstract: A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process.

Abstract: A multi-frequency receiver for detecting the presence of one or more of a plurality of m frequency tones in an incoming signal. A digital signal processor executes a fast algorithm for accurately calculating the spectral energies in a plurality of m frequency bands. Each frequency band is centered on one of the frequencies to be detected. The center frequencies of those bands are independent of the data length used. The calculated spectral energies are compared to a set of predefined thresholds. As a result, the presence of particular tones within the incoming signal are detected.

Abstract: A coding and decoding apparatus for an acoustic signal obtained by extracting a series of sampled acoustic signal data as a series of frames. From data obtained over each of a predetermined number of discrete frequencies by implementing orthogonal transform processing to acoustic signal data using the same window function for first and second frames in sequential frames of the acoustic signal having a predetermined fixed time length, phase information for each of the discrete frequencies is obtained for every first and second frames. Then, quantities of changes in the phase information of each one of the discrete frequencies in the first frame with respect to the corresponding frequencies in the second frame are determined.

Abstract: In a method of recording data on an optical card having a plurality of tracks, each track consisting of a plurality of lines and a guide pattern, the data is divided into thirteen packets 1P to 13P each having thirty-four bytes, corresponding bytes in all the packets are grouped to form thirty-four divisions each having thirteen bytes, each of the bytes in respective divisions is divided into lower significant four bits and higher significant four bits to form sixty-eight frames, and all bits in respective frames are rearranged in the order of significance to form in-line interleaved bit data. The thus formed in-line interleaved bit data is recorded in a predetermined line in a predetermined track on the optical card, while the recording operation is controlled by a clock signal which is derived by optically reading the guide pattern formed in the relevant track. In this manner, the data is interleaved among the single line, and thus the recording operation can be performed at a high speed.

Abstract: A detector for determining the validity of a received code, such as a Digital Supervisory Audio Tone (DSAT) code. A received DSAT code is serially shifted into a shift register (10) which outputs the received DSAT code in parallel format to a set of 24 exclusive-OR gates (12). Another shift register (11) receives a valid code, such as a valid DSAT code. The register (11) outputs the valid DSAT code, and right circular shifted (rotated) versions of the valid DSAT code, to the gates (12). The comparison signal from the gates (12) is provided to another register (13) and a counter (16) which together count the number of mismatches between the received DSAT code and the reference DSAT codes. The output of the counter (16) is provided to a comparator (17) which compares the number of mismatches against the allowable number of mismatches. The output of the comparator (17) is a validity signal (7) which indicates whether the received DSAT code matches any of the reference DSAT codes.

Abstract: The amplitude or frequency of a sinusoidal signal represented as sample values S.sub.1, S.sub.2, S.sub.3, S.sub.4 is estimated by computing a triplet of differences x.sub.1, x.sub.2, x.sub.3, where x.sub.1 is a difference between S.sub.2 and S.sub.1, x.sub.2 is a difference between S.sub.3 and S.sub.2, and x.sub.3 is a difference between S.sub.4 and S.sub.3. An indication of the estimate of the amplitude or frequency is computed as a ratio of algebraic functions of the differences x.sub.1, x.sub.2, x.sub.3. The amplitude is computed as the square root of a first ratio of algebraic functions, and the frequency is computed as an arc-cosine function of a second ratio of algebraic functions. Preferably the ratio is evaluated by a division operation computed as a polynomial approximation, and the square root function and the arc-cosine function are also computed as a polynomial approximation. Preferably ratios computed from a plurality of triplets are averaged together to give more accurate estimates.

Abstract: An automatic pattern synchronizing circuit re-times the phase differences between clocks, thereby adjusting test pattern outputs from a device under test. The automatic pattern synchronizing circuit includes a reference voltage generator for providing a threshold voltage, a comparator for converting an input signal into a rectangular signal, a flip-flop, a pattern-counter part for counting a signal from the flip-flop and a control part for setting the threshold voltage in the comparator. The automatic pattern synchronizing circuit automatically synchronizes voltage patterns. In particular, the high and low voltage levels of the input waveform are automatically measured and the optimum threshold voltage is automatically set.

Abstract: A programmable controller having a word processor for word processing operations and a bit processor for bit processing operations. The bit processor has a first flag register and a second flag register which permit the comparison of the results of word processing operations with the results of the preceding bit processing operations to be simplified.

Abstract: The invention includes an arrangement of actual sensors in an antenna array with a computation of higher-order statistics to provide virtual second order statistics corresponding to virtual elements in the array; employment of the actual and virtual elements of the array for covariance based direction finding; and, with the addition of a separate sensor spaced from the main array, suppression of non-Gaussian measurement noise. This is accomplished employing cross-correlation of the virtual sensors or alternately calibrating the existing actual array employing cross-correlation of the array and it's virtual sensors.

Abstract: An electronic component with a shift register test architecture (boundary scan) includes test cells. A register cell in a test cell is programmable with a manufacturer datum.