Abstract: Image sensor structures are provided. In some embodiments, an image sensor structure is provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate and extending from the top surface to the bottom surface of the substrate. The image sensor structure further includes a first isolation structure extending from the top surface of the substrate to a middle portion of the substrate and a second isolation structure formed extending from the bottom surface of the substrate to the middle portion of the substrate and in contact with the first isolation structure. The image sensor structure further includes a gate structure overlapping the light-sensing region, the first isolation structure, and the second isolation structure and a cap layer overlapping the gate structure, the light-sensing region, the first isolation structure, and the second isolation structure in a top view.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

Abstract: A semiconductor device includes a semiconductor part, a first electrode and control electrodes at the front side of the semiconductor part. The semiconductor part includes first to fourth layers, first and third layers being of a first conductivity type, second and fourth layers being of a second conductivity type. The control electrodes are provided in a plurality of trenches, respectively. The control electrodes include a first control electrode, and a second control electrode next to the first control electrode. The second layer is provided between the first layer and the first electrode. The third and fourth layers are provided between the second layer and the first electrode. The semiconductor part further includes a first region partially provided between the first and second layers. The first region is provided between the first and third layers, the first region including a material having a lower thermal conductivity than the first layer.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A MOSFET device arranged on a substrate 10 having first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on the substrate 10, the channel being covered by a dielectric layer 20, itself surmounted by a third contact 21. The channel 18 incorporates a thin film 19 lightly doped with dopant atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

Abstract: A display device includes a base layer including a pixel area, and a pixel in the pixel area. The pixel includes a first area, and a second area enclosing the first area in a plan view, bank patterns at the pixel area, extending in a first direction, spaced from each other by a first distance in the first area, and spaced from each other by a third distance that is greater than the first distance in the second area, a first electrode and a second electrode at an area of the bank patterns, and spaced from each other by a second distance that is less than the first distance in the first area, a first insulating layer at a portion of the pixel area including the first area to cover the first electrode and the second electrode and removed from another portion of the pixel area including opposite edge portions.

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

Abstract: An image sensing device comprising a plurality of unit photosensing pixels to convert light into electrical signals, each unit photosensing pixel including a photosensor and a plurality of transistors to perform operations associated with the photosensor and a plurality of protection devices, each of which is coupled to any one of the plurality of transistors, wherein each of the plurality of protection devices includes a first region doped with a first type of conductive impurities, a second region doped with a second type of conductive impurities and surrounding the first region, and a third region doped with the first type of conductive impurities and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and is coupled to any one of the plurality of transistors.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

Abstract: A display device includes a substrate. The substrate includes a display area and a non-display area, and the display area includes an emission area and a non-emission area. A display element layer includes a light emitting element on the emission area of the substrate. A bank is on the display element layer and overlaps the non-display area and the non-emission area of the substrate in a plan view. A color conversion layer is on the display element layer, overlaps the emission area in the plan view, and is to convert a color of light emitted from the light emitting element. An organic insulating layer is on the color conversion layer and the bank. A maximum thickness of the bank is about 4 ?m to about 20 ?m. An average inclination angle of a first side surface of the bank adjacent to an edge of the substrate in the non-display area based on an upper surface of the substrate is less than or equal to about 45 degrees.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Abstract: A display device includes a display portion mounted with a first LED and a second LED are mounted, a pixel circuit portion provided with a first pixel-circuit thin film transistor electrically connected to the first LED and a second pixel-circuit thin film transistor electrically connected to the second LED, a drive circuit portion provided with a drive-circuit thin film transistor, and a shielding layer provided between the display portion and the drive circuit portion. A fixed potential is applied to the shielding layer. The second LED overlaps the drive circuit portion with the shielding layer therebetween.

Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.

Abstract: A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.