Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A MOSFET device arranged on a substrate 10 having first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on the substrate 10, the channel being covered by a dielectric layer 20, itself surmounted by a third contact 21. The channel 18 incorporates a thin film 19 lightly doped with dopant atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

Abstract: An image sensing device comprising a plurality of unit photosensing pixels to convert light into electrical signals, each unit photosensing pixel including a photosensor and a plurality of transistors to perform operations associated with the photosensor and a plurality of protection devices, each of which is coupled to any one of the plurality of transistors, wherein each of the plurality of protection devices includes a first region doped with a first type of conductive impurities, a second region doped with a second type of conductive impurities and surrounding the first region, and a third region doped with the first type of conductive impurities and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and is coupled to any one of the plurality of transistors.

Abstract: A display device includes a base layer including a pixel area, and a pixel in the pixel area. The pixel includes a first area, and a second area enclosing the first area in a plan view, bank patterns at the pixel area, extending in a first direction, spaced from each other by a first distance in the first area, and spaced from each other by a third distance that is greater than the first distance in the second area, a first electrode and a second electrode at an area of the bank patterns, and spaced from each other by a second distance that is less than the first distance in the first area, a first insulating layer at a portion of the pixel area including the first area to cover the first electrode and the second electrode and removed from another portion of the pixel area including opposite edge portions.

Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

Abstract: A display device includes a display portion mounted with a first LED and a second LED are mounted, a pixel circuit portion provided with a first pixel-circuit thin film transistor electrically connected to the first LED and a second pixel-circuit thin film transistor electrically connected to the second LED, a drive circuit portion provided with a drive-circuit thin film transistor, and a shielding layer provided between the display portion and the drive circuit portion. A fixed potential is applied to the shielding layer. The second LED overlaps the drive circuit portion with the shielding layer therebetween.

Abstract: A display device includes a substrate. The substrate includes a display area and a non-display area, and the display area includes an emission area and a non-emission area. A display element layer includes a light emitting element on the emission area of the substrate. A bank is on the display element layer and overlaps the non-display area and the non-emission area of the substrate in a plan view. A color conversion layer is on the display element layer, overlaps the emission area in the plan view, and is to convert a color of light emitted from the light emitting element. An organic insulating layer is on the color conversion layer and the bank. A maximum thickness of the bank is about 4 ?m to about 20 ?m. An average inclination angle of a first side surface of the bank adjacent to an edge of the substrate in the non-display area based on an upper surface of the substrate is less than or equal to about 45 degrees.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.

Abstract: A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A display apparatus including a plurality of pixel regions disposed on a support substrate, each of the pixel regions including a plurality of subpixel stacks including a first epitaxial stack, a second epitaxial stack, and a third epitaxial stack, in which light generated from the first epitaxial stack is to be emitted to the outside of the display apparatus through the second and third epitaxial stacks, light generated from the second epitaxial stack is to be emitted to the outside of the display apparatus through the third epitaxial stack, during operation, one of the subpixel stacks within each pixel region is configured to be selected and driven, and at least one subpixel stack further includes an electrode disposed between the first epitaxial stack and the support substrate to be in ohmic contact with the first epitaxial stack.

Abstract: A pixel includes a light emitting area including a central portion and an outer portion, a non-light emitting area surrounding the light emitting area, a first electrode and a second electrode that are spaced apart from each other in the light emitting area, and a first light emitting element disposed between the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other at a first interval in the central portion, and are spaced apart from each other at a second interval in the outer portion. The second interval is larger than the first interval. An interval between the first electrode and the second electrode gradually increases from the central portion to the outer portion.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.