Abstract: A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the top portion. The inner portion contains the p-type impurity element and, in combination therewith, hydrogen.

Abstract: A ferroelectric integrated circuit including a substrate supporting a thin film ferroelectric material and an electrode layer in contact with the ferroelectric material, the ferroelectric material comprising a compound including a metal element, the electrode comprising the metal element. The metal element of the ferroelectric material may exist in the electrode in the pure metal form, as an alloy, as part of a crystalline compound, or as part of an amorphous material. The electrodes may be formed by a single layer, or as multi-layer structures, providing the layer adjacent the ferroelectric contains at least one of the metal elements of the ferroelectric. The electrode is formed at the eutectic temperature of its constants.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: When static electricity having an excessive voltage is applied to a VSS terminal, the static electricity may be transmitted to an inner cell directly connected to a VSS cell before the static electricity is discharged to the outside via an electrostatic protection circuit, possibly resulting in electrostatic destruction. Bypasses are thus provided to bypass the static electricity applied to a VSS terminal to a higher wiring layer, which allow only excessive static electricity to be selectively discharged to the outside via an electrostatic protection circuit.

Abstract: A semiconductor device comprises a plurality of superposed layers including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermined layer, the dummy pattern being formed on an inner side of a dicing region. The ratio of an area of the dummy pattern in a planar region defined by the inner edge of the dummy pattern, the outer edge of the dicing region and two optional, parallel lines to that of the planar region is 50% or above.

Abstract: A MONOS memory transistor capable of high speed write with a small current and superior in scaling, comprised of substrate (well W), a channel forming region, a first and a second impurity regions SBLi, SBLi+1 comprised of an opposite conductivity type semiconductor and sandwiching the channel forming region between them and acting as a source and a drain in operation, gate insulating films 10a, 10b, 14 and gate electrode WL on the channel forming region, and a charge storing means (carrier trap) which is formed in the gate insulating films 10a and 10b and dispersed in the plane facing the channel forming region and in the direction of thickness and is injected with hot holes caused by a band-to-band tunnel current from the impurity regions SLi or SLi+1 in operation.

Abstract: A CMOS image sensor is provided with a first pixel group 12 and a second pixel group 13. The first pixel group 12 composed of a plurality of pixels arranged in a matrix at specified pitches PH and PV in the horizontal and vertical directions, respectively. The second pixel group 13 composed of a plurality of pixels arranged similarly in a matrix shifted by about one-half of the pitches PH and PV in the horizontal and vertical directions, respectively from the matrix of the first pixel group. Each of these pixels is composed of a combination of a photodiode PD, a reset transistor RS, a driver transistor D and an address transistor AD. The reset transistors RS belonging to the first and second pixel groups 12, 13 and arranged in a corresponding row of the matrix are connected to a common reset line RSL. Similarly, the address transistors AD belonging to the first and second pixel groups 12, 13 and arranged in a corresponding row of the matrix are connected to a common address line ADL.

Abstract: A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Abstract: A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first, fluorine is implanted in the first polysilicon layer to form the floating gate. It is disclosed here that the implanting of fluorine increases the oxidation rate of the polysilicon and because of the faster oxidation, the polygate bird's beak that is formed attains a relatively short and sharp in comparison with conventional beaks. This has the attendant benefit of forming a relatively small memory cell, and the concomitant reduction in the erase speed of the cell. In the second embodiment, oxygen is used with the same favorable results. A third embodiment discloses the structure of a split-gate flash memory cell having a sharp bird's beak.

Abstract: A semiconductor memory device has gate electrodes which are formed on a gate insulating film in direct contact therewith and have nitrogen-doped regions on their sides, or gate electrodes which use a nitrogen-doped polysilicon film. The widthwise end portions of the gate electrodes are located outward of the associated end portion of a semiconductor substrate under the gate electrodes and extend over device isolation regions. This structure can suppress a variation in the threshold voltages of memory cells when the semiconductor memory device operates. It is therefore possible to provide a highly reliable nonvolatile semiconductor memory device.

Abstract: There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.

Abstract: The present invention provides a semiconductor device including a first gate—gate electrode layer located in a first conductive layer and including gate electrodes of a first load transistor and a first driver transistor and a second gate—gate electrode layer located in the first conductive layer and including gate electrodes of a second load transistor and a second driver transistor. A first drain—drain connecting layer is located in a second conductive layer which is an upper layer of the first conductive layer and connects a drain of the first load transistor with a drain of the first driver transistor. A second drain—drain connecting layer is located in the second conductive layer and connects a drain of the second load transistor with a drain of the second driver transistor.

Abstract: A passive device and module for a transceiver, and a manufacturing method thereof are provided. The passive device includes a semiconductor or a dielectric substrate, at least one capacitor, at least one inductor, a viahole, a metal electrode, radio frequency signals, a radio frequency ground, a packaging substrate. The at least one capacitor is formed on a first surface of the substrate. The at least one inductor is formed on a second surface of the substrate that is opposite to the first surface. The viahole penetrates through the substrate. The metal electrode is formed on the viahole and electrically connects the capacitor on the first surface and the inductor on the second surface. Radio frequency signals are for the inductor and the capacitor. The radio frequency ground is formed on the substrate and isolated from the radio frequency signals.

Abstract: A ferroelectric capacitor adapted for a non-volatile semiconductor memory comprises a base substrate with an insulating surface, such as a semiconductor substrate formed with semiconductor elements and having a top insulator film, a lower electrode formed on the insulating surface, an oxide ferroelectric layer formed on the lower electrode, a first oxide upper electrode formed on and in contact with the upper surface of the oxide ferroelectric layer, and a second oxide upper electrode formed on the first oxide upper electrode, wherein one of the first and second oxide upper electrodes comprises SRO that laminating a first and a second oxide upper electrodes onto said oxide contains at least 0.1 at % additive and the other of the first and second oxide upper electrodes comprises IrOx. A non-volatile semiconductor memory or ferroelectric capacitor, having a PZT ferroelectric layer, excellent in characteristics, and capable of being manufactured efficiently, is provided.

Abstract: A first capacitor electrode and at least part of a second capacitor electrode of a capacitor are produced in depressions of an auxiliary layer by electroplating. The auxiliary layer is then removed and at least partially replaced by a capacitor dielectric. The first capacitor electrode and the part of the second capacitor electrode may be composed of a metal, for example platinum. The capacitor dielectric can be composed, for example, of barium-strontium-titanate.

Abstract: An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

Abstract: A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high adhesive strength to the gate insulating film is disposed. The polysilicon side wall (5) is brought into a close contact with the tungsten nitride (6b) on the side surface of the tungsten (6c). With this structure improved is adhesive strength of a metal wire or a metal electrode which is formed on an insulating film of a semiconductor device.

Abstract: In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (&mgr;m) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23).

Abstract: A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.