Abstract: A method that finds all test vectors for all detectable single stuck-at faults in a combinational circuit during a single pass through the circuit sorts a netlist into circuit-level order, provides a library of fault-propagation and path-enabling rules for the circuit's logic elements, begins at the level of the primary inputs, and applies the rules, one logic element at a time, circuit-level-by-circuit-level until the entire circuit has been processed. The resulting fault-propagation functions for each output line define every combination of primary input signals that makes a fault detectable at that output line. In another embodiment, the method determines the highest circuit level at which each signal is used, and releases storage being used for previously computed fault-propagation functions and path-enabling functions for any signal having no further uses. The elimination of no longer needed stored information permits the method to handle larger circuits given finite resources.

Abstract: A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.

Abstract: Method and apparatus for testing the operation of an integrated circuit (IC) while maintaining the supply input to the IC constantly active during the test. A logic indication signal that provides a first logic level indicating the active state of the supply input and a second logic level indicating the inactive state of the supply input, is generated. The inactive state of the supply input is simulated by processing the first logic level and by generating a third logic level that is essentially similar, or identical, to the second logic level. The third logic level is applied to one or more signal-carrying contacts within the IC and these, or other, signal-carrying contacts within the IC are accessed and their corresponding signal values responsive to the applied third logic level are read. One or more read signal values are compared with the one or more values expected for such readings.