Abstract: The present disclosure provides a secondary battery, which comprises a cap plate, at least two cells and two connecting pieces. The cap plate is provided with two electrode terminals which are opposite in electrical polarity. Each cell has two tabs which are opposite in electrical polarity. Each connecting piece has: an electrode terminal electrical connecting portion for electrically connecting with the corresponding electrode terminal of the cap plate; a plurality of tab electrical connecting portions for electrically connecting with the corresponding tabs of the cells respectively; and a plurality of fusing portions electrically connecting the corresponding tab electrical connecting portion to the electrode terminal electrical connecting portion, a width of each fusing portion is less than a width of the electrode terminal electrical connecting portion. A configuration of the connecting piece is simple, thereby reducing the cumulative heat of the secondary battery and reducing the temperature rise.

Abstract: A scaffold-free 3D porous electrode comprises a network of interconnected pores, where each pore is surrounded by a multilayer film including a first layer of electrochemically active material, one or more monolayers of graphene on the first layer of electrochemically active material, and a second layer of electrochemically active material on the one or more monolayers of graphene. A method of making a scaffold-free 3D porous electrode includes depositing one or more monolayers of graphene onto a porous scaffold to form a graphene coating on the porous scaffold, and depositing a first layer of an electrochemically active material onto the graphene coating. The porous scaffold is removed to expose an underside of the graphene coating, and a second layer of the electrochemically active material is deposited onto the underside of the graphene coating, thereby forming the scaffold-free 3D porous electrode.

Abstract: An assembled battery includes a cell stack formed by stacking a plurality of unit cells in the same direction, positive electrode-side bus bars respectively connected to positive electrode tabs of the unit cells, and negative electrode-side bus bars respectively connected to negative electrode tabs of the unit cells. A positive electrode-side bus bar connected to a positive electrode tab of a first unit cell of adjacent unit cells in the cell stack, and a negative electrode-side bus bar connected to a negative electrode tab of a second unit cell, are connected to each other on one of the surfaces of the cell stack.

Abstract: According to one embodiment, there is provided an active material. The active material includes particles of a Na-containing niobium titanium composite oxide having an orthorhombic crystal structure. An intensity ratio I1/I2 is within a range of 0.12?I1/I2?0.25 in an X-ray diffraction pattern of the active material, according to X-ray diffraction measurement using a Cu-K? ray. I1 is a peak intensity of a peak P1 that is present within a range where 2? is 27° to 28° in the X-ray diffraction pattern of the active material. I2 is a peak intensity of a peak P2 that is present within a range where 2? is 23° to 24° in the X-ray diffraction pattern of the active material.

Abstract: Disclosed is a process for one-step preparing electrolyte used for lithium-iron(II) disulfide batteries. The process includes the following steps of: adding iodine-containing precursors into an organic solvent in an inert atmosphere, homogeneously stirring, then adding lithium-containing precursors, stirring and reacting, separating solids to obtain an electrolyte used for lithium-iron(II) disulfide batteries. The process involves one-step synthesizing electrolyte used for lithium-iron(II) disulfide batteries. The whole procedures do not introduce water and have a lower cost. The lithium-iron(II) disulfide batteries prepared by using the electrolyte prepared by the process of the present invention have better properties.

Abstract: An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connectes to the functional input and output signal leads, core circuitry (120, 122, 124), and interconnect wires and circuits (103) connecting the input and output circuits and the core circuitry. The integrated circuit further includes an addressable test port (105, 115, 135) for each core circuitry. Each test port is connected to its respective core circuitry and to the interconnect wires and circuits. External test signal leads (106) connectes to each test port.

Abstract: An integrated circuit device includes a package and an externally accessible signal lead attached to the package. An integrated circuit chip is mounted in the package and connected to the signal lead. The integrated circuit chip includes a mode-selective signal generating circuit configured to receive a mode control signal and an internal signal and coupled to the externally accessible signal lead. The mode-selective signal generating circuit is operative to produce an output signal responsive to one of the internal signal or an external signal applied to the externally accessible signal lead based on the mode control signal. According to an embodiment, the integrated circuit chip further includes a memory circuit including a sense amplifier that senses a bit line voltage in response to a sense enable signal. The internal signal includes a sense enable control signal having a timing adapted for sensing a bit line voltage in a memory cycle of the memory circuit.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.

Abstract: A semiconductor integrated-circuit device includes both conventional internal circuitry, and a selection circuit that provides external output of signals from the internal circuitry under control of a selection signal. In a parallel test system, the output terminals of a plurality of devices under test are connected to a single set of tester input terminals, at which response signals are received from each device in turn. Alternatively, each device has an internal test circuit that carries out tests in response to test control codes received from a tester, evaluates the response signals from the internal circuitry, makes a pass/fail decision, and provides the tester with the pass/fail result.

Abstract: A test pattern generator for automatically generating a test pattern for detecting a stack fault of a large scale integrated circuit an LSI with a tester includes a loop/path disconnecting section for disconnecting a loop portion of the LSI at a position where a fault detection rate is not lowered, based on net list information of the LSI and constraint of a test design rule when automatically generating the test pattern. A test pattern generator increasing fault detection rate and carrying out a suitable test is obtained.

Abstract: A DVD-ROM data decoding processing system includes a DVD-ROM reproducing unit 32 and a buffer memory 34. The DVD-ROM reproducing unit 32 includes a demodulating part 36, a PI syndrome generating part 38, an error correcting part 40, a buffer memory 42 having a memory capacity corresponding to a few lines, a PO syndrome generating part 44, a descrambling/EDC calculating part 46, a PI syndrome storing memory 48, a PO syndrome storing memory 50, an EDC calculation result storing memory 52, an error correcting part 54, and a CPU 56. The error correcting part 40 derives the position and the magnitude of errors in the PI series from the PI syndromes generated in the PI syndrome generating part 38, and corrects the data errors in the buffer memory 42 on the basis of the position and the magnitude of errors in the PI series, interleave by interleave.

Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Abstract: A node controller (12) includes a local block unit (28) that receives and processes request and reply packets. A request module (30) in the local block unit (28) receives a request packet and determines whether the request packet has an error. If there is no error, the request module (30) forwards local invalidation requests to a invalidation module (32) for processing and forwards programmed input/output read and write requests to a processor module (34) for processing. If an error is detected, the request module (30) forwards the request packet to a registers module (40). The registers module (40) stores the header and data contents of the request packet in header registers (70, 72) and a data register (80). An error bit is corresponding to the identified type of error is set in an error register (50). The request module (40) generates an interrupt signal (52) in response to setting the error bit in the error register (50).

Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Abstract: A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a pair of global error correction codes, referred to generally as an untwisted global error correction code and a twisted global error correction code. Data at corresponding bit positions within the logical groups are conveyed through a common component. The untwisted global error correction code may be equivalent to the result of generating an individual error correction code for each logical group and XORing the collection of individual error correction codes together.

Abstract: Test sequences for use in fault testing for an integrated circuit are efficiently generated. The integrated circuit is subjected to timeframe expansion, thereby generating a time expansion model including a combinational circuit. With respect to this time expansion model, a compaction template is generated by compacting one or more primitive templates indicating whether or not a primary input or a pseudo primary input is present in each time. Test patterns are generated with respect to the time expansion model, and the generated test patterns are transformed, with compaction accompanied, into test sequences. The compaction is conducted by substituting the respective test patterns in the compaction template and connecting the resultant compaction templates. In this manner, short test sequences can be efficiently generated without spending much time on the compaction.

Abstract: LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.

Abstract: A method for detecting faulty equipment on a loop of disk drives in which error counts are obtained for each disk drive including an amount of invalid transmission words and/or a count of loop initialization protocols (LIPs) that have been initiated and received. Counts are obtained twice so as to detect changes to the error counts. Based on the error counts and LIP counts suspect disk drives may be recorded along with their electrical predecessor on the loop to permit expedited identification of faulty equipment.

Abstract: A method of testing memory of a system is disclosed which operates the system from a second area of system address space which is outside of a first area of system address space, the system having one or more physical memory devices associated with the first area of system address space. The memory locations associated with the first area of the system address space are tested for predetermined characteristics after which the one or more tested physical memory devices are replaced with respective untested physical memory devices without dropping power to the system, and tested by repeating the test cycle. The system is prevented from operating in the first area of system address space and forced to operate from the second area, thereby preventing system interruptions when replacing the physical memory devices for testing.

Abstract: An optical filter comprises a transparent and a filter layer. The filter layer contains a dye and a binder polymer. The dye is a cyanine dye represented by the formula (I). The filter layer further contains a specific metal complex. in which each of Z1 and Z2 independently is an non-metallic atomic group forming a five-membered or six-membered nitrogen-containing heterocyclic ring; each of R1 and R2 independently is an alkyl group, an alkenyl group, an aralkyl group or an aryl group; L1 is a methine chain consisting of an odd number of methines; X is an anion; and each of a, b and c independently is 0 or 1.