Patents Examined by Cynthia R Harris
  • Patent number: 6463560
    Abstract: A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: October 8, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sudipta Bhawmik, Indradeep Ghosh, Niraj Jha
  • Patent number: 6415399
    Abstract: A test pattern generation circuit for generating a test pattern for a disturb test is provided in an SDRAM. A test pattern generated in the test pattern generation circuit is supplied to a circuit relating to a selected bank and a test pattern is supplied from a tester to a circuit relating to other bank. As more than one test can be simultaneously performed, test time can be reduced.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: July 2, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigeru Yamaoka