Abstract: An semiconductor assembly includes at least one die having substantially planar first and second engagement surfaces and external edges which define a die shape. A base having an opening formed therein receives the die. The base opening has peripheral edges which define an opening shape and size which is complementary to the die external shape. The opening edges engage the die edges to spatially fix the die in a selected orientation in a plane parallel to the die first planar engagement surface. An interconnecting plate has at least one substantially planar engagement surface facing the first planar engagement surface of the die received within the base opening. At least one conductive pad on the plate planar engagement surface is spatially aligned or registered with a corresponding conductive pad on the first engagement surface of the die.

Abstract: A DRAM having stacked capacitor cell comprises one transfer gate transistor and one capacitor. A thick insulating film having flat surface is formed on the surface of the transfer gate transistor and the like. A conductive film is formed on a surface of one impurity region of the transfer gate transistor. An opening portion deep enough to reach the conductive film is formed in the insulating film. The capacitor is formed in the opening portion and on the upper surface of the insulating film. A lower electrode of the capacitor is connected to the conductive film. An insulating film having a flat surface is formed by a reflow process employing thermal processing, plasma ECR CVD method and the like.

Abstract: A semiconductor device comprising one conductivity type semiconductor substrate, a reverse conductivity type diffusion layer, a semiconductor wiring layer and a metal connection wiring layer, and said metal connection wiring layer is composed of a high melting metal film formed by a selective CVD method.

Abstract: A semiconductor memory device which is provided with a groove type capacitor and which has been improved for increasing its storage capacity without lowering the degree of integration, and the method for producing the memory device. The device includes a first capacitor including a storage node (16) formed on the inner wall of the groove (15), a capacitor insulating film (20) and a cell plate electrode (22), a second capacitor including an electrically conductive member (43) provided on the perimeter of the groove (15), the capacitor insulating film (20) and the cell plate electrode (22). The semiconductor memory device has its storage capacity increased by an amount corresponding to the capacity of the second capacitor. The degree of integration is not lowered in any way since the electrically conductive member (43) forming the second capacitor is provided on the groove (15) perimeter.

Abstract: A leadframe including a die pad and inner leads the die pad having a substantially rounded edge configuration with no sharp edge, and the inner leads each having a trapezoidal cross-sectional configuration. In this construction, stresses are not concentrated in the end portion of the die pad due to temperature stresses and therefore, no cracks are formed in the resin encapsulating ICs. Accordingly, highly reliable ICS can be provided.

Abstract: Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.

Abstract: A semiconductor device structure comprises a semiconductor substrate having a semiconductor layer of the same conductivity type formed on its first surface. A drain contact is formed on the second surface of the substrate and conductive regions having the opposite conductivity type of the substrate are formed in the semiconductor layer and are separated by a predetermined distance. Channel regions having the same conductivity type as the substrate are disposed above the conductive regions and source regions are disposed therein. A shielding region is then formed on the surface of the device structure in the area between the conductive regions. The structure allows for reduced or eliminated gate-drain capacitance, reduced output conductance and increased breakdown voltage capability.

Abstract: In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode makes contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Since both the upper surface and the lower surface of the charge storage electrode are utilized for the formation of the capacitor, the size of the capacitor can be halved to produce the same capacitance.

Abstract: An integratable power transistor with optimization of direct secondary breakdown phenomena which comprises a plurality of elementary transistors which are arranged side by side and comprise a plurality of cells, each of which is formed by an emitter reigon surrounded by base and collector regions, with the emitter regions arranged physically separated. According to the invention, the base regions are also arranged physically separated and are mutually connected by resistive elements.

Abstract: A semiconductor device includes an n.sup.+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n.sup.+ layer without alloying, and an externally accessible base region produced in the neighborhood of the emitter electrode by a diffusion using the emitter electrode and an insulating side wall film as a diffusion mask.

Abstract: A semiconductor device is provided which comprises a single crystalline substrate having a main surface, an insulating layer formed on the main surface of the single crystalline substrate, and a semiconductor region of a single crystal formed on the insulating layer, wherein the semiconductor region has top and bottom surfaces and a thickness of not more than 6 .mu.m and an impurity is doped in the semiconductor region from the top to bottom surfaces thereof, a concentration of the impurity gradually decreasing from the top to bottom surfaces, whereby the semiconductor region is made a first conductivity type by the doped impurity. The semiconductor device further comprises an insulating gate type field effect transistor including source and drain regions in the semiconductor region, the source and drain regions having a conductive type opposite to that of the first conductivity type, and further there is provided a process for manufacturing such a semiconductor device.

Abstract: A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing difffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.

Abstract: A trimming resistor element includes a high-resistance film of high resistivity formed on an insulation film on the main surface of a substrate, and a low-resistance region which is formed by selectively subjecting the high-resistance film to a predetermined process so as to lower the resistivity thereof. A resultant resistance of the low-resistance region and the high-resistance film can be adjusted by selectively cutting off part of the low-resistance region.

Abstract: A lateral transistor with a fine structure includes a semiconductor substrate of one conductivity type on which a mesa-shaped projection of opposite conductivity type is provided. The projection has side walls opposed to each other and serves as a collector region. A base region of one conductivity type is provided in one side wall of the projection, while a collector contact region is provided in the other side wall thereof. An emitter region of opposite conductivity type is also formed in the base region. A base contact layer of polysilicon is provided on a field oxide layer and is in contact with the base region at the edge. In the same manner, a collector contact layer of polysilicon provided on the field oxide layer is in contact with the collector contact region at the edge.

Abstract: In a pressure-contacted large-area power semiconductor element, in which a substrate (1) is compressed between an anode-side (20) and a cathode-side compression plate (19), an improved contact is obtained by arranging, at least between one of the compression plates (19,20) and the associated contact (2,9), a metal foil (17) which is soldered to this contact.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.

Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Abstract: A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode.

Abstract: A semiconductor power switching device has an insulated gate which establishes charge carrier flow between an additional terminal and a base region to provide current flow through the device between collector and emitter terminals. The device in effect comprises a bipolar transistor with an integral MOSFET for driving its base, so that a small signal applied to the gate drives the bipolar transistor into saturation. In use the collector is connected to a supply rail through a load and the additional terminal is connected directly or indirectly to the same rail.

Abstract: A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.The modified fabrication steps are readily integrable in a normal CMOS fabrication process.