Abstract: A solid state logical "AND" circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.

Abstract: A TTL circuit comprising an inverted signal output transistor (Tr.sub.4) and an off buffer circuit (Tr.sub.2, Tr.sub.3), alternately turned on and off in response to an input signal, to provide an inverted output. According to the invention, two driving circuits for driving the inverted signal output transistor and the off buffer circuit are separately provided. The threshold voltage of the circuit for driving the off buffer circuit is lower than the threshold voltage of the circuit for driving the inverted signal output transistor, whereby no transient current flows through the off buffer circuit and the inverted signal output transistor.

Abstract: A clock circuit for producing a high-level delayed clock output following an input clock employs an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.

Abstract: A three-state MOS circuit for buffering an input signal includes an edge definition circuit which is controlled by first and second independent clock signals. The edge definition circuit includes a first transistor for producing a low-to-high voltage transition when the input signal goes from a high to a low, and a second transistor for producing a high-to-low voltage transition in response to the input signal going from a low to a high. The generation of these high-to-low and low-to-high transitions are controlled by first and second independent clock signals. The output of the edge definition circuit is applied to a driver circuit which generates output control signals. The output control signals are applied to first and second output field effect transistors so as to generate a signal representative of the input signal.

Abstract: A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits including a 4:1 multiplexer and a comparator of two three-digit binary numbers. The logic gate advantageously is formed in a silicon chip which includes an array of cells each consisting essentially of nine single-emitter transistors, two four-emitter transistors and a number, advantageously nine, of resistors.