Abstract: A circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures. In one procedure, control of memory is transferred only after a request for memory access has been made. In a second procedure, transfer of memory control to a requesting processor is automatically accompanied by a request to return control. The control memory of a processor selects the process by two bits called Code Idle and Code Release. Code Idle accompanies instructions that usually mean that the releasing processor will not need memory for several memory cycle times, and an explicit request for transfer is made when memory is actually needed. Code Release accompanies instructions that do not require memory access at the time but are typically followed by a memory request within a processor cycle time or a few processor cycle times. Memory control is returned without the delay that is associated with an explicit request.