Abstract: An integrated circuit semiconductor device in which a first insulating layer including a silicon nitride film and a second insulating layer including a silicon oxide film thermally grown are formed on a major surface of a silicon substrate and contacted each other at respective side edges to form a boundary is disclosed. First and second electrodes are formed on the first and second insulating layers, respectively and separated each other with a gap. A third insulating layer fills the gap and contacts to both of peripheral surface sections of the first and second insulating layers extending from the boundary, respectively.

Abstract: A protection circuit including complementary bipolar transistors having collectors connected to an input and base and emitters connected together to a respective voltage source. The bipolar transistors are lateral transistors having a field plate over the base region and spaced laterally from the laterally spaced collector and emitter regions. The base may include increased impurity surface regions extending from the emitter and collector to the gate to increase the beta and decrease the collector-base breakdown.

Abstract: A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film.

Abstract: A bipolar semiconductor device with interdigitated emitter and base regions has a sub-region of the base, which has a shorter carrier recombination time than the major part of the base region due to the presence of argon ion implantation induced carrier recombination centers. The sub-region of the base is located centrally with respect to the emitter region to intercept the transient current lines during device turn-off and so to promote collapse of the transient current and the avoidance of second breakdown of the device. The centrally located sub-region of the base is remote from the emitter region edges to collector region current flow when the device is on. The ions may be implanted at energies between 50 keV and 3 MeV and at doses between 10.sup.11 ions cm.sup.-2 and 10.sup.14 ions cm.sup.-2. The implanatation mask may be provided by photolithographically processed resist having a thickness between 0.5 .mu.m and 4 .mu.m dependant on the ion implantation energy.

Abstract: A photoelectric conversion device having electric conversion cells capable of performing a store operation, a read operation and a refresh operation. In the store operation, a potential of a control electrode region of a semiconductor transistor is controlled using a capacitor and carriers are stored, which carriers have been generated by light excitation at the control electrode region. In the read operation, a signal under control of a voltage generated by the stored carriers is read out of a main electrode area of the semiconductor transistor. In the refresh operation, carriers stored in the control electrode region are removed. A semiconductor region of the same conductivity type as the main electrode region, is formed in the control electrode region separately from the main electrode region.

Abstract: A redundant circuit of a semiconductor device comprises a fuse (73) for laser trimming to connect between aluminum interconnections (6). The fuse (73) has a two-layer structure comprising a first film (3a) of polysilicon and a second film (7a) formed on the film (3a) of metal silicide, the line width l.sub.0 of the first film (3a) being shorter than the line width l.sub.1 of the second layer (7a). In addition, a PSG film (4) is formed to cover the fuse (73), and the laser beam is irradiated on the PSG film (4) in disconnecting the fuse (73). Accordingly, the first film (3a) having a short line width is uniformly fused and expanded, the fuse (73) is uniformly disconnected, and an opening (10) formed after explosion and splash thereof becomes smaller.

Abstract: The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region.

Abstract: In the CMOS semiconductor device having an epitaxial layer, a trench with an appropriate depth is formed in the vicinity of a boundary between a range in which a MOS transistor is formed and a well range in which another MOS transistor is formed; the inner wall surface of the trench is covered with a thermal oxide film; and the trench is buried with a semiconductor substance, so that two CMOS transistors can be electrically isolated by the trench to increase the latch-up holding voltage beyond a supply voltage (e.g. 5 v). Therefore, the latch-up proof resistance can be increased to protect the device from noise which otherwise would break the device. Further, the trench depth is shallower than the low impurity atom concentration layer (epitaxial layer) or 3 .mu.m but deeper than a value obtained by subtracting 2 .mu.m from the above thickness or 3 .mu.m.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention). A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: A heterojunction-gate field-effect transistor comprises an active layer of semiconductor material having source and drain regions, an intermediate layer of another semiconductor material formed on the active layer between the source and drain regions, the intermediate layer inducing a two-dimensional charge layer in a surface portion of the active layer between the source and drain regions, and a gate electrode of a mixed semiconductor crystal formed on the intermediate layer to control the conductivity of the two-dimensional charge layer by an electrical potential applied thereto. The mixed semiconductor crystal may be GaP-InAs or mixed crystal of GaP-InAs mixed crystal and AlP-GaAs, AlsB-GaP, or GaSb-GaP mixed crystal.

Abstract: An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.

Abstract: An optical signal processor which comprises a phototransistor for receiving optical signals and an input for receiving external electrical signals, a plurality of base regions connected, respectively, to the phototransistor and the input, for accumulating charges corresponding to the optical signals and the external electrical signals, and a gate electrically coupled thereto an insulating layer to the base regions to control the transfer of charges between them so as to permit mixing of optical and external electrical signals.

Abstract: A bipolar transistor susceptible to high level integration has its active regions formed in slots within a semiconductor substrate. In one embodiment, the emitter is formed within a slot and has a surrounding region doped to function as a base. A collector is formed in another slot which is located adjacent but spaced apart from the emitter slot. Carrier transport occurs principally horizontally between the emitter and base and then to the collector. Additional slots may be used to isolate the slot transistor in conjunction with a horizontally disposed pn junction and a buried collector. The collector may be formed in a slot which contains an oxidized outer sidewall that serves to isolate the individual transistor.

Abstract: A semiconductor device including an input circuit, in which an impurity region is formed in a semiconductor substrate under the input circuit. This impurity region has a conductivity type opposite to that of the substrate or at least has a lower impurity concentration than that of the substrate. According to this structure, the input voltage capability of the device is improved. Additionally, the fabrication methods of this semiconductor device are disclosed.

Abstract: For decreasing a leakage current, there is disclosed a protective network fabricated on a semiconductor substrate for preventing a protected node from a destruction comprising, a semiconductor substrate of a first conductivity type, an insulating film overlying the semiconductor substrate, a first impurity region of a second conductivity type formed in the semiconductor substrate and providing a signal path with a relatively large resistance value electrically connected at a contact portion thereof to the protected node, the signal path having an upstream portion and a downstream portion providing between the contact portion and the upstream side portion, a second impurity region of the second conductivity type formed in the semiconductor substrate and electrically connected to a constant voltage source, a separating region defined in the semiconductor substrate and intervening between a part of the first impurity region and the second impurity region for causing the part of the first impurity region to be sp

Abstract: A ROM circuit is used in place of a conventional fuse type ROM which is incorporated in a semiconductor integrated circuit network together with other circuit blocks on a chip. The ROM circuit comprises a first transistor having a control and a floating gate and a depletion type second transistor having a gate formed as an extension of the floating gate. The second transistor outputs a high level control signal if hot electrons have been accumulated on the floating gate of the first transistor by the application of a predetermined high level input signal to the control gate thereof, and outputs a low level signal when the high level input signal has not been provided to the control gate. The first transistor is freed from a soft write problem because it is separated from a voltage source in the read mode.

Abstract: A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.

Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.

Abstract: A semiconductor integrated circuit device comprising: at least two NPN transistors whose bases and emitters are connected to the ground and whose collectors are connected to an input terminal; one of said NPN transistors having a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said NPN transistors; and an input portion which has a breakdown maintaining voltage at a high surge voltage breakdown which occurs caused by an application of a high surge voltage input to said input terminal which is lower than that at a low input voltage breakdown which occurs caused by an application of a low surge voltage or an input voltage which rises up gradually.

Abstract: Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together.