Abstract: Frame information is recovered from a stream of binary data formed at a transmitter from a block of m.times.n information bits comprising m groups of n bits plus m parity bits, one for each said group of n bits, these parity bits having then been scrambled by performing an exclusive-OR operation in a gate on each parity bit with a respective bit of an m-bit parity scrambling code, said block of bits together with the scrambled parity bits forming a frame for transmission over a transmission link. At a receiver new parity bits are produced in a parity bit generator at the incoming bit rate from the incoming stream of binary data by forming a new parity bit from each successive moving group of n+1 incoming bits. The new parity bits are cyclically distributed to n+1 m-bit shift registers and a framing signal is produced when one of the shift registers holds m bits substantially corresponding to the m bits of the parity scrambling code.

Abstract: A data processing system is disclosed in which it is detected whether or not data to be read out from a buffer memory with a single access are spread over a plurality of blocks, which are used as the unit for storing data in the buffer memory, and, when the presence of block cross is detected, addresses of blocks including a desired operand are generated as addresses in banks making up the buffer memory, whereby the operand is read out from adjacent blocks by a single read-out operation.

Abstract: A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a "window" on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer.

Abstract: Direct connect devices such as cathode ray tube displays are coupled to a communications controller through a long cable and a flexible line adapter package. Apparatus in the controller generates a clocking signal which is applied to a Universal Synchronous Receiver Transmitter (USRT) and to the direct connect device. The USRT receives data from a microprocessor and transmits a stream of data signals synchronized to the clocking signal. The data signals and the clocking signals are received by the direct connect device. The clocking signals strobe the data signals approximately in the center of a data pulse since transmission delays for the data signals and the clocking signals are approximately equal.

Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Abstract: A programmable controller has a scanner module that couples a main processor through two multidrop serial data channels to a relatively large number of remotely located I/O interface racks. The main processor executes a control program to examine input status data coupled from I/O devices on a controlled system through the I/O interface racks and determines output status data which is coupled through the I/O interface racks to control output devices on the controlled system. The scanner circuit encodes a stream of output status data by generating an output mask work and the adapter circuit encodes a stream of input status data by generating an input mask word, the mask words being appended to streams of status data that are coupled to and from each rack in serial data messages.

Abstract: A surge counter for a rotating compressor is provided which detects surging by monitoring the vibration signal from an accelerometer mounted on the shaft bearing of the compressor. The circuit detects a rapid increase in the amplitude envelope of the vibration signal, e.g., 4 dB or greater in less than one second, which is associated with a surge onset and increments a counter. The circuit is rendered non-responsive for a period of about 5 seconds following the detection which corresponds to the duration of the surge condition. This prevents multiple registration of counts during the surge period due to rapid swings in vibration amplitude during the period.