Abstract: There is disclosed an integrated circuit package assembly for housing an integrated circuit die wherein the integrated circuit package assembly affords substantially reduced ground bounce within the integrated circuit. The package assembly includes a planar electrically conductive sheet upon which the integrated circuit die is insulatively bonded. The integrated circuit package includes at least one ground lead which is coupled to a conductive ground pad on the integrated circuit by a first ground wire which connects the ground pad to the electrically conductive sheet and a second bond wire which connects the electrically conductive sheet to the ground lead. The assembly is completed by an encapsulation which encapsulates the integrated circuit die, the electrically conductive sheet, the first and second bond wires, and a portion of the ground lead.

Abstract: A solid state imaging device has solid-state imaging-device chips each having a picture-element array and bonding pads, chip carriers each having long sides longer than the solid-state imaging-device chip and terminals electrically connected to corresponding bonding pads on the chip, a package board which carries the chip carriers, and external leads provided on the package board and electrically connected to the respective terminals of the chip carriers. In a method of assembling such a solid state imaging device, a plurality of solid-state imaging-device chips are mounted on respective chip carriers, and a plurality of imaging units are formed by electrically connecting the terminals of each chip carrier to the corresponding bonding pads. The imaging units are then arranged on the package board and the terminals of the imaging units are connected to the external leads, respectively.

Abstract: This invention is basically related to an insulated gate bipolar transistor comprising a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the substrate and having a low concentration of impurities, a first conductivity type base layer formed on a surface of the semiconductor layer, a second conductivity type source layer formed on the surface of the base layer and having a channel region at at least one end thereof, a gate electrode, a source electrode and a drain electrode, and is characterized in that a voltage dropping portion is provided either inside the source layer or between the source layer and the source electrode. Accordingly an insulated gate bipolar semiconductor transistor having this configuration can prevent a latch up phenomenon caused by a voltage drop in a source layer.

Abstract: In a semiconductor element having a semiconductor body, an electrode structure is arranged on at least one major surface of the element for storing charge carriers of at least one conductivity in cells formed by the electrode structure. Control electrodes which are at least partially enclosed in the semiconductor body are arranged in at least one plane essentially parallel to the major surface of the semiconductor body. The control electrodes similarly enable charge carriers to be stored in defined cells. The control electrodes stored also make it possible to shift stored charges from one cell to another, whereby at least two independent charge images can be stored in a three-dimensionally arranged storage cell pattern.

Abstract: In a depletion mode thyristor of the type including a regenerative portion and a non-regenerative portion, the turn-off time for the thyristor is substantially reduced without producing a corresponding increase in the on-resistance of the device by providing a region of relatively low carrier lifetime in the non-regenerative portion of the device in the layer or layers in which charge storage limits the turn-off time for the device. Turn-off of the thyristor is accomplished by pinching off the regenerative portion, thereby diverting current into the low carrier lifetime non-regenerative portion.

Abstract: Flexible cooling paths are connected to semiconductor elements which are heated members. A cooling apparatus comprises cooling blocks connected to cooling blocks, coolant flow paths through which the coolant flows, coolant branching mechanisms provided in the coolant flow paths and connecting mechanism for connecting the branching mechanism and the cooling blocks through O-rings. A part of coolant flowing through the cooling flow paths is introduced into the cooling blocks for the respective heated chips in order.

Abstract: A semiconductor integrated circuit device of multi-layer interconnection structure includes a pad formed of a multilayer interconnection layer. The power source pad is connected to a power source interconnection layer via a lead-out interconnection layer which is formed of the same multilayer interconnection layer as that used to form the power source pad.

Abstract: A semiconductor package having a gull-wing, zig-zag, inline-lead configuration and end-of-package anchoring devices for rigidly affixing the package to a circuit board such that each lead is in compressibe contact with its associated mounting pad on the board. The anchoring devices of a first embodiment comprise anchoring pins having fish-hook-type barbs which lock against the under side of the board when the pegs are inserted through holes in the board; a second embodiment utilizes anchoring pins which are adhesively bonded in recesses that have been drilled or molded into the board; a third embodiment utilizes anchoring pins, the ends of which can be bonded directly to planar peg-bonding regions on the surface of the board; and a fourth utilizes tapered anchoring ping which may be inserted with an interference fit into holes in the board. The invention eliminates the need for mechanical support of the packages during solder reflow operations used during board assembly and repair.