Abstract: Process for the preparation of thin moncrystalline or polycrystalline semiconductor material films, characterized in that it comprises subjecting a semiconductor material wafer having a planar face to the three following stages: a first stage of implantation by bombardment (2) of the face (4) of the said wafer (1) by means of ions creating in the volume of said wafer a layer (3) of gaseous microbubbles defining in the volume of said wafer a lower region (6) constituting the mass of the substrate and an upper region (5) constituting the thin film, a second stage of intimately contacting the planar face (4) of said wafer with a stiffener (7) constituted by at least one rigid material layer, a third stage of heat treating the assembly of said wafer (1) and said stiffener (7) at a temperature above that at which the ion bombardment (2) was carried out and sufficient to create by a crystalline rearrangement effect in said wafer (1) and a pressure effect in the said microbubbles, a separation between the thin film

Abstract: A method of producing sharp points on the surface of a substrate is described. The points are useful as field emitter tips, and may also be used to collect radiant energy and for the production of micromachined objects such as micron sized gears and levers. Conventional techniques of asperity fabrication typically use an undercut of a hard mask to etch away the substrate material. This conventional method is very time specific and difficult to control. The inventive process uses a more easily controlled etch than conventional asperity fabrication techniques. The inventive process begins with a substrate highly doped with a P-type dopant such as boron which prevents an etch with KOH or other material. A hard mask is patterned over the substrate surface, and an N-type dopant, such as phosphorous or arsenic, is implanted into the substrate surface. The N-type dopant diffuses under the hard mask at a rate more easily controlled than the etch used in conventional techniques.

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.