Abstract: It is intended to provide a recording-medium operating device, a clock signal generating device for the recoding-medium operating device, and a method for generating a clock signal for the recoding-medium operating device that satisfy both operation with a wide-range data transfer rate using delay line provided with not so large number of stages and high correction accuracy and are advantageous in terms of low power consumption and suppression of noises. A reference clock group Ø0 through Øx different in phase are obtained by a PLL 1. One of the reference clock group is selected by a clock selector 2. A selected clock signal is inputted to a delay circuit 3 and one of output clocks from a delay line 31 is selected by a selector 3. With structure as such, selection by the clock selector 2 and the selector 3 is controlled so as to make phase difference between a clock signal and an RF signal minimum.