Patents Examined by D Nhu
  • Patent number: 6423645
    Abstract: The present invention discloses a method for forming a self-aligned contact. In the present invention, a amorphous SiC layer or a HexaChloroDisilane-SiN (HCD-SiN) layer is formed on the surface of a transistor as an etching stopper layer. After removing part of the etching stopper layer, a gate protection film is formed on the surface of the gate electrode of a transistor. Due to the high etching selectivity of the gate protection film to the dielectric layer, the gate protection film effectively prevents the gate electrode of a transistor from being etched in the contact-etching process. In addition, the gate protection film has a low dielectric constant thereby reducing the parasitic capacitance of a bit line formed by the self-aligned contact forming method according to the present invention.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: July 23, 2002
    Assignee: Mosel Vitelic Inc.
    Inventors: Houng-chi Wei, Tsong-lin Shen
  • Patent number: 6136727
    Abstract: In a method for forming a thermal oxide film of a silicon carbide semiconductor device, a preliminary treatment is conducted in which a silicon carbide substrate is heated to 800 to 1200.degree. C., in an atmosphere comprising hydrogen or a mixture of hydrogen and inert gas, and then a silicon dioxide film is formed on the substrate by thermal oxidation. A slight amount of hydrochloric acid gas may be added to the atmosphere for the preliminary treatment.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: October 24, 2000
    Assignee: Fuji Eletric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 6130111
    Abstract: A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: October 10, 2000
    Assignee: NEC Corporation
    Inventors: Kazuhiro Ikuina, Yuzo Shimada, Kazuaki Utsumi
  • Patent number: 6087260
    Abstract: A method for manufacturing a bit line. A substrate having a dielectric layer on the substrate and a contact hole penetrating through the dielectric layer and exposing portions of the substrate is provided. A patterned conductive layer is formed on the dielectric layer and fills the contact hole. The surface of the patterned conductive layer is converted into an oxide layer. The oxide layer is removed. A silicide layer is formed on the patterned conductive layer.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: July 11, 2000
    Assignee: United Semiconductor Corp.
    Inventor: Hsiu-Wen Huang