Abstract: The present invention is related to bus extender circuitry for data transmission from a first bus at a first site to a second bus at a second site, includes a first transceiver at the first site, a second transceiver at the second site and a data and control signals transmission medium interconnecting both transceivers. The first transceiver receives data signals and interacts by means of control signals with the first bus which has data and control lines connected to a data source and possibly also to one or more receivers all located at the first site. The second transceiver receives data signals and interacts, by means of control signals, with the first transceiver to transmit data and control signals to the second bus; the second transceiver has data and control lines connected to one or more receivers at the second site.

Abstract: A microprogram controller, in a microcomputer system used as an address sequencer intended for controlling the sequence of execution of microinstructions in a microprogram memory, is presented. The microprogram controller includes architecture that provides the capability to asynchronously receive indications of an event, break from the microinstruction sequence in response, branch to control of subroutine consisting of a predetermined microinstruction sequence directed to responding to the event, and returning to the interrupted sequence upon completion of the subroutine.

Abstract: In a system including a single main storage or memory and two or more processing units sharing the main storage or memory, there are provided two address arrays for storing the addresses of the data of the main storage or memory which is stored in a buffer storage or memory, one address array storing the same addresses as those stored in the other address array. One of the address arrays is used for reference to the buffer storage or memory by the own or associated processing unit, while its other address array is used for detecting that the store address from another processing unit to the main storage or memory is coincident with one of the addresses stored therein. When the coincidence of addresses is detected, the corresponding address in the other address array is invalidated or cancelled, and the roles of the two address arrays are interchanged. Subsequently, the corresponding address in the one address array is invalidated cancelled.

Abstract: A function presetting circuit for an audio/video stereophonic playback system for presetting a function and controlling operations by a microcomputer comprises a reset circuit for providing a reset signal to the microcomputer at a time of power-on, a delay circuit for receiving the reset signal and delaying the reset signal a predetermined time period, and a presettable function presetting switch connected between the delay circuit and a key input terminal of the microcomputer.

Abstract: Record data on a disk file is sorted in a text/data processor by means of an algorithm that transfers such records on the basis of rank to a sort buffer on the basis of qualifying criteria. Each qualified file record is compared with the lowest ranked record previously transferred and located in the sort buffer. When a higher ranked record is identified it is transferred into the buffer at a location based on qualification. Lower ranked records are deleted from the sort buffer if space does not permit the storing of such records within the space available. When the sort buffer has been loaded with the highest ranked records remaining in the disk file without overflowing the buffer is unloaded to an output device. The sort program recycles through a subsequent pass again transferring the highest ranked remaining records into the sort buffer. To minimize recycle time, a presort algorithm is run to set record identifying bits in a bit map section of the sort buffer.

Abstract: The use of protected capability registers to hold the physical base and limit addresses and access rights for a block of memory and the way in which such registers are loaded using System Capability Tables and reserved segment pointer tables is well known in the prior art. In the present invention the normal capability load instruction has been enhanced in four major ways:(a) allowing additional capability classes to be handled(b) instituting a "load on use" facility(c) instituting capability propagation control and(d) implementing access reduction facilitiesThe capability classes comprise (i) system store, (ii) system resource, (iii) local store and (iv) passive capability. The "load on use" facility speeds up the load capability instruction and the change process instruction.

Abstract: A micro-sequencer allowing multiple decisions to be made in one instant of time is disclosed. A multiplexor array is employed to generate a multiple output condition code from inputted test conditions. The generated condition code is concatenated to a base pointer field of the currently executing microinstruction, and the result is used to address a next state table. The output of the next state table is the address of the microinstruction to be executed next if the then currently executing microinstruction specifies a jump operation.

Abstract: A circuit arrangement is provided for controlling the drive of dental treatment instruments by means of driving devices associated therewith and the operating data of which are adapted to be fed to a separate forward/backward counter when the particular treatment instrument is selected for use. A starter switch is connected to the forward/backward counter and is operable, when actuated, to vary the particular stored count of the counter step-wise for the purpose of varying the operating data and for transmission to a control element, for the control thereof, which is associated with the particular treatment instrument. Upon actuation of the starter switch in order to vary the stored count of the forward/backward counter, the counting speed of the counter is increased with increasing actuation time of the starter switch by reason of the fact that the counter receives a number of counter pulses which increase per unit time.