Abstract: An apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus. Latching means and gating means are coupled to CPU and the output ports to control the clock signal received. The input port receives a change frequency signal. In response, the CPU executes the instructions from the instructing means to store the contents of the CPU's internal registers into memory. The CPU then generates a frequency select signal and a reset signal that resets itself. The latch means stores and outputs the frequency select signal to the gating means. The gating means uses the frequency select signal to output one of a plurality of different frequency clock signals received at its select input as the operating clock input of the CPU. The CPU thereafter operates under the newly gated clock signal. After the CPU reset is complete, the CPU reloads its internal registers with the information stored within the memory.

Abstract: VGA controller interface circuitry that allows the VGA controller to reduce the cycle time of a write to the controller below the default write cycle time, resulting in a significant improvement of the controller's performance. The controller interface circuitry uses a Zero Wait State control signal on the system bus to reduce the cycle time by overriding the default cycle time for a memory write, unless the /Ready signal is asserted by the controller.

Abstract: A modified IEEE 488.1 bus interface increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices involved in a particular data transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller software in that it does not require any changes to the controller software nor to the device drivers and device application programs.