Patents Examined by D. Sparks
  • Patent number: 6910105
    Abstract: When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5).
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: June 21, 2005
    Assignee: Terminus Technology Limited
    Inventor: Naoyuki Ogura
  • Patent number: 5719749
    Abstract: A printed circuit assembly includes a fine pitch flexible printed circuit overlay bonded to a normal pitch printed circuit board. The fine pitch flexible printed circuit overlay may provide increased packaging density, direct chip attachment and/or complex routing with a minimal cost impact on the overall printed circuit assembly.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: February 17, 1998
    Assignee: Sheldahl, Inc.
    Inventor: Jahn J. Stopperan
  • Patent number: 5432679
    Abstract: An integrated circuit chip module assembly (10) is disclosed that electrically interconnects the bond pads of the various integrated circuit chips (20) in the module to circuitry (42) on a thin film multilayer membrane (22). The module assembly includes a heat sink (16) with the back surfaces of the chips (20) in thermal engagement therewith. Contacts (40) of the bond pads of the chips (20) are in electrical engagement with the circuitry (42) on the membrane (22) and are accurately positioned by means of nests (28) formed on the surface of the membrane (22). A contact pressure equalizer (12) engages only selected areas (98) of the membrane (22) opposite the contacts (40) of the chips (20) to urge the contact surfaces (44) on the membrane (22) into electrical engagement with raised contacts (40). The contact pressure equalizer (12) includes a relatively large pressure plate (70) having a layer (74) of relatively soft rubber thereon.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: July 11, 1995
    Assignee: The Whitaker Corporation
    Inventor: Dimitry G. Grabbe
  • Patent number: 5430616
    Abstract: An interconnector includes a first connecting portion connected to a front surface electrode of a solar cell, a second connecting portion connected to a rear surface electrode of another solar cell connected in serial direction, and a stress relief portion formed between the first connecting portion and the second connecting portion for absorbing displacement. The width of the first connecting portion in the parallel direction is made smaller than the width of the stress relief portion in the parallel direction. By this structure, the width of the front surface electrode of the solar cell can be reduced, the effective light receiving area of the solar cell can be increased, and therefore the efficiency in generating power can be improved.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: July 4, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoji Katsu, Keiji Shimada, Hideki Yoshioka
  • Patent number: 5412541
    Abstract: A sheet member adapted for attachment to an acoustic or imaging apparatus to improve the acoustic or imaging performance thereof. The sheet member is generally circular, including a plurality of generally W-shaped cut-outs and a like plurality of generally V-shaped cut-outs both formed alternately and equi-angularly in the outer circumference thereof. The sheet member improves the acoustic or imaging performance by reducing the interference caused by electromagnetic radiations emitted from the acoustic or imaging apparatus or their components to which the sheet member is attached. The reduction of such interference can be attained also by forming a compact disc, a laser disc, a magnetic tape, a semiconductor chip, a circuit board, a magnetic or IC card or the like in a manner to have such cut-outs in their outer circumference.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: May 2, 1995
    Inventor: Tatsuo Tanaka
  • Patent number: 5404274
    Abstract: An assembly for mounting a circuit board between spaced surfaces is disclosed. The assembly includes a housing and a circuit board retainer including a protrusion. The housing is designed and constructed to receive and retain a fully assembled circuit board retainer. The housing includes at least one pair of channel walls defining a channel for receiving an end of the protrusion. The channel walls are constructed to permit movement of the protrusion into and out of the housing when a force in a proper direction above a predetermined threshold is applied to the protrusion.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: April 4, 1995
    Assignee: EG&G Birtcher, Inc.
    Inventors: Raymond G. Bond, Conrad Hulme
  • Patent number: 5383093
    Abstract: A multilayer substrate is constituted by laminating a plurality of sheet substrates, the respective sheet substrates are constituted by forming conductive layers of a refractory metal such as tungsten (W) on ceramic green sheets composed mainly of an alumina ceramic, and the ceramic green sheets are laminated and sintered to constitute the multilayer substrate. Conductive material layers are formed on the surface of the multilayer substrate so as to be selectively connected to the conductive layers, and copper-plated layers are formed on the conductive material layers. Thick film conductor layers are formed on the copper-plated layers, to constitute terminal conductors, and, a thick film resistor layer for example is connected to the terminal conductors.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: January 17, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventor: Takashi Nagasaka
  • Patent number: 5377079
    Abstract: An electronic device comprises a housing made of a polycarbonate resin, and a novel double-sided printed circuit board. The printed circuit board has one side embedded in the housing, and the other side exposed to the interior of the housing. A plurality of refractory electronic components are mounted onto one side of the printed circuit board and include a resistor and a capacitor. A plurality of lower refractory electronic components are mounted onto the other side of the housing and include a semiconductor integrated circuit, and a transformer. Preferably, an insulating layer is applied to cover the one side of the printed circuit board and the refractory electronic components. Also, a metal layer is applied to cover the insulating layer and the inner surface of the housing.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: December 27, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeshi Morita, Osamu Hayashi
  • Patent number: 5359497
    Abstract: A planar triode is mounted in a PC board orifice by means of a U-shaped capacitor housing and anode contact yoke removably attached to cathode leg extensions passing through and soldered to the cathode side of the PC board by means of a PC cathode pad. A pliant/flexible contact attached to the orifice make triode grid contact with a grid pad on the grid side of the PC board, permitting quick and easy replacement of bad triodes.
    Type: Grant
    Filed: May 10, 1993
    Date of Patent: October 25, 1994
    Assignee: Regents of the University of California
    Inventor: Rex Booth
  • Patent number: 5339220
    Abstract: A host structure (P) is provided for terminal adaptors (AD-AD.sub.14, SDI) of a distributed information processing architecture (ARCH) having information processing systems (SI, SI.sub.1, SI.sub.j, . . . , SIS.sub.j, SAD, . . . SAD.sub.j) which communicate by way of a network (RE). The host structure (P) includes a first compartment (CAV) containing a plurality of cartridges (1, AD-AD.sub.14, ADI) each containing a board carrying the electronic circuit of an adaptor, a second compartment (CAR) containing the electrical supply to the boards contained in the first compartment and a ventilation device (VAT) of the structure. The first and second compartments are separated by a backpanel (FP) carrying a copper bus (BCE, BCE.sub.j) specific to the network to which the boards carrying the terminal adaptors are connected. The backpanel (FP) includes a CORE (CF-CF.sub.14) for connecting the boards to the network (RE) and to the bus (BCE), on the one hand, and to the power supply (AIM), on the other.
    Type: Grant
    Filed: August 19, 1992
    Date of Patent: August 16, 1994
    Assignee: Bull, S.A.
    Inventors: Antoine Chotard, Jean-Jacques Belloir, Thierry Iceta
  • Patent number: 5319524
    Abstract: A card cage formed of mating, identical halves provides parallel slots for circuit boards carrying snap-on retainer clips with integral pawl-like clasps which lock over ridges on the exterior of the card cage. The clip is released from the cage by squeezing the clasps with one hand before withdrawing the circuit board. Slotted side brackets capture mating ribs on the card cage halves to assemble and mount the card cge to a wiring clost panel.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: June 7, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Glenn S. Welch, Stephen A. Fidrych, Michael Romm
  • Patent number: 5313369
    Abstract: A simple, low cost, reduced tolerance interconnect enclosure in which a blind m A siVpV:interconnect between modules and the backplane may be guaranteed without the need for assembly fixtures or floating connectors, and a method of manufacturing the enclosure. The enclosure includes two matching enclosure sections for holding a backplane. The backplane has spaced apart recesses on opposing edges. Each enclosure section includes alignment protrusions spaced apart to engage the backplane recesses. These protrusions have curved apex regions and a height greater than the depth of the backplane recesses. Means for latching the enclosure sections together are provided, and the enclosure sections are dimensioned such that when the enclosure sections are closed around the backplane, the protrusions from the enclosure sections are urged against the recesses on the backplane.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: May 17, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Mark S. Lewis, Lori A. Treseder, Reuben Martinez, Ralph M. Tusler
  • Patent number: 5268819
    Abstract: A printed circuit board upon which are mounted a number of electronic components is provided with a connector strip for electrically coupling the components to respective components on a second circuit board located underneath. The strip comprises a body portion and pins projecting thereform. The pins have a stepwise configuration with a first end portion extending through apertures in the upper circuit board and connected to a second connector strip on the second circuit board, a second end portion extending through the body portion, and a middle portion which abuts the surface of the upper circuit board and by which the strip is connected to the upper circuit board by means of a solder joint. Components on the upper circuit board are electrically coupled by means of tracks which are connected to the components at one end by a solder joint and at the other end by a solder joint, via pins, to the second connector strip and tracks on the lower circuit board.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: December 7, 1993
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Pekka S. Lonka
  • Patent number: 5264990
    Abstract: The invention relates to an integrated circuit card comprising a card support (130) which has a cavity (101) in which a vignette (200) is fixed, which vignette (200) comprises a circuit support (20, 40) and a circuit (10) arranged on a lower surface of the circuit support facing towards the interior of the cavity (101), the circuit (10) being positioned opposite a portion of a bottom (100) of the cavity (101). The bottom (100) has at least two weakenings (104) situated on either side of a bridge-portion (103) of the bottom.
    Type: Grant
    Filed: May 9, 1991
    Date of Patent: November 23, 1993
    Assignee: U.S. Philips Corporation
    Inventor: Jacques Venambre
  • Patent number: 5258892
    Abstract: A communication device (10) includes a loop antenna (18) that is located within a molded portion of the housing (14) of the communication device, and an electrical contact (20) for the antenna that also provides a mechanical support for at least a portion of the communication device (10).
    Type: Grant
    Filed: January 22, 1992
    Date of Patent: November 2, 1993
    Assignee: Motorola, Inc.
    Inventors: Stephen M. Stanton, Rudy Yorio
  • Patent number: 5255161
    Abstract: Wire guide element for a distributor unit in telecommunication systems. The plug connector strips of the distributor unit are secured to the edges of a vertically aligned U-shaped carrier part. A hollow plastic member is used as a wire guide element for the lines proceeding between neighboring distributor units arranged at both sides. With the guide peg present at the under side, this hollow plastic member is plugged, on the one end, onto the upper edge of the leg of the carrier part and, on the other hand, is snapped onto the retainer plate joined in this region to the carrier part at the back side. At least one hook attached to the upper side parallel to the plate also serves for the ordered guidance of lines. At its front side, the hollow member has a slot specifically designed for the insertion of lines.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: October 19, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Knoll, Peter Stoerk
  • Patent number: 5243499
    Abstract: Distributor unit for attaching and connecting electrical lines in telecommunication systems. A rail (5) is secured in two different positions in a simple manner from a servicing side and is provided for the acceptance of accessory equipment (15). The two positions are in the upper end region of the carrier part (1) vertically aligned with its long side in that the rail (5) is hooked to or, respectively, plugged onto the upper edge of a plate (4) that is rigidly connected to the carrier part (1). The edge of the plate (4) provided for the plug fastening of the distributor unit extends beyond the upper edge of the carrier part (1) in a longitudinal direction. Different accessory equipment is easily attached to the front side of the rail independently of the wiring of the distributor. The parts of the distributor normally covered by the planar extent of the rail toward the servicing side are accessible at any time in the respectively other position of this rail.
    Type: Grant
    Filed: December 5, 1991
    Date of Patent: September 7, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Knoll, Peter Stoerk
  • Patent number: 5241455
    Abstract: To minimize the area of an L-shaped channel wiring region between VLSI circuit blocks, a trunk 1 is formed in the direction along L-shaped sides A and B in the wiring region interposed between the L-shaped sides A and B of circuit blocks CB1 and CB2 having terminals on their sides. The trunk 1 is converted into a polygonal line so as to occupy two tracks. The polygonal line is obtained by combining a line segment in the direction along the L-shaped sides A and B with a line segment parallel to the middle angle direction D of an L-shaped angle.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: August 31, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Fukui, Yoshiyuki Kawakami
  • Patent number: 5241456
    Abstract: An improved high density interconnect structure may include electronic components mounted on both sides of its substrate or a substrate which is only as thick as the semiconductor chips which reduces the overall structure thickness to the thickness of the semiconductor chips plus the combined thickness of the high density interconnect structure's dielectric and conductive layers. In the two-sided structures, feedthroughs, which are preferably hermetic, provide connections between opposite sides of the substrate. Substrates of either of these types may be stacked to form a three-dimensional structure. Means for connecting between adjacent substrates are preferably incorporated within the boundaries of the stack rather than on the outside surface thereof.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: August 31, 1993
    Assignee: General Electric Company
    Inventors: Walter M. Marcinkiewicz, Charles W. Eichelberger, Robert J. Wojnarowski
  • Patent number: RE34887
    Abstract: A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.
    Type: Grant
    Filed: April 10, 1991
    Date of Patent: March 28, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Ushifusa, Hiroichi Shinohara, Kousei Nagayama, Satoru Ogihara, Tasao Soga