Patents Examined by D. Tran
  • Patent number: 6244043
    Abstract: A nitrous oxide trap temperature control system for desulfating the trap uses and engine with some cylinders operating with lean combustion and some cylinders operating with rich combustion. The lean and rich combustion gases are combined to form an mixture which is fed to the trap to provide an exothermic reaction. The desired lean and rich air/fuel ratios of the respective lean and rich cylinders are determined based in part on the difference between the trap temperature and a desired trap temperature. The desired lean and rich air/fuel ratios of the respective lean and rich cylinders are also determined from the desired mixture air/fuel ratio entering the trap.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: June 12, 2001
    Assignee: Ford Global Technologies, Inc.
    Inventors: David George Farmer, Gopichandra Surnilla, Jerry Dean Robichaux, Salomone Castro
  • Patent number: 5754814
    Abstract: A accordance determining circuit (113) that determines whether or not a cache address CA required in updating a cache data memory (111) and a cache tag memory (112) accords with the address of data read from an external memory (130) is provided. When the accordance determining circuit (150) has determined an accordance state, a register (115) is enabled so that cache data read from the external memory (130) is stored in a register (115) and supplied to a cache requester (101). Alternatively, a means for generating an address corresponding to the next data of data to be updated in updating the cache data memory (111) and (112) is provided so as to determine the cache status of an address being generated. Thus, if the determined result represents that the cache data has not been stored, a plurality of data are updated at a time. Consequently, the mis-hit penalty time can be reduced and the hit ratio can be improved.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: May 19, 1998
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kazuhiko Maki
  • Patent number: 5517662
    Abstract: A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processors is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviors in the protocol when message packets depart or when they arrive.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: May 14, 1996
    Assignee: International Business Machines Corporation
    Inventors: John J. Coleman, Ronald G. Coleman, Owen K. Monroe, Robert F. Stucke, Elizabeth A. Vanderbeck, Stephen E. Bello, John R. Hattersley, Kien A. Hua, David R. Pruett, Gerald F. Rollo