Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

Abstract: A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.

Abstract: The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.

Abstract: A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

Abstract: The present application provides a backside illuminated CMOS image sensor and a method of making the same. The backside illuminated CMOS image sensor comprises: a pixel region substrate, an isolation structure, a first dielectric layer, a metal grid, and second dielectric layer, wherein grid trenches and a metal plug are formed in the pixel region substrate, the isolation structure is located in each of the grid trenches and on the surface of the pixel region substrate outside of the grid trenches, and the isolation structure comprises a high-K dielectric layer, an insulating layer, and a metal core layer.

Abstract: According to the present disclosure, hybrid fins positioned between two different epitaxial source/drain features are recessed to prevent conductive material from entering interior air gaps of the hybrid fins, thus, preventing short circuit between source/drain contacts and gate electrodes. Recessing the hybrid fins may be achieved by enlarging mask during semiconductor fin etch back, therefore, without increasing production cost.

Abstract: A display device includes a substrate including a pixel area, and a pixel disposed in the pixel area and including an emission area and a non-emission area. The pixel includes a first alignment electrode and a second alignment electrode spaced from each other on the substrate, an insulating layer disposed on the first and second alignment electrodes, at least one light emitting element disposed on the insulating layer between the first alignment electrode and the second alignment electrode in the emission area, a pattern disposed between the at least one light emitting element and the insulating layer and including a hydrophilic group, and a bank disposed on the insulating layer in the non-emission area and including a first opening corresponding to the emission area and a second opening spaced from the first opening of the bank.

Abstract: A semiconductor storage device according to an embodiment includes a stacked body and a pillar. The pillar includes an insulating core, a channel layer, and a memory film. A plurality of gate electrode layers included in the stacked body includes a plurality of first gate electrode layers and one or more second gate electrode layers. The channel layer includes a first portion and a second portion. The first portion is provided between an uppermost first gate electrode layer and the insulating core. The second portion extends from a first height to a second height. A film thickness of the second portion is greater than a film thickness of the first portion.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A photoelectric conversion apparatus according to an embodiment includes a first chip and a second chip. The first chip includes a first semiconductor element layer having a pixel region having pixel circuits and a peripheral region and a first wiring structure including a first wiring layer. The second chip includes a second semiconductor element layer having an electric circuit and a second wiring structure. The first and second chips are stacked, and have a trench extending through the first semiconductor element layer and having a pad through which a reference potential is supplied to the pixel circuits. The first wiring layer includes a first wiring pattern to which the reference potential is supplied. In plan view, the first wiring pattern located in a region aligned with the pixel region has a higher wiring density than the first wiring pattern located in a region aligned with the peripheral region.

Abstract: Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.

Abstract: A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.

Abstract: A display device includes a first light emitting element, a second light emitting element, and a third light emitting element that are disposed on a substrate and emitting light of different colors, respectively; a first insulation layer disposed on the first light emitting element, the second light emitting element, and the third light emitting element, and including at least one opening; and a second insulation layer disposed on the first insulation layer, and disposed in the at least one opening, wherein a refractive index of the second insulation layer is higher than a refractive index of the first insulation layer, and the at least one opening overlaps at least one of the first light emitting element, the second light emitting element, and the third light emitting element in a plan view, and does not overlap at least another one in a plan view.