Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

Abstract: According to an embodiment, a film formation apparatus and a film formation method that can form GaN film with high productivity are provided. The film formation apparatus includes: the chamber which an interior thereof can be made vacuum; the rotary table provided inside the chamber, holding a workpiece, and circulating and transporting the workpiece in a circular trajectory, a GaN film formation processing unit including a target formed of film formation material containing GaN and a plasma generator which turns sputtering gas introduced between the target and the rotary table into plasma, the GaN film formation processing unit depositing by sputtering particles of the film formation material containing GaN on the workpiece circulated and transported by the rotary table; and a nitriding processing unit nitriding particles of the film formation material deposited on the workpiece circulated and transported by the rotary table in the GaN film formation processing unit.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixel blocks arranged in a matrix form. Each of the unit pixel blocks includes a plurality of imaging pixel groups and a cross-talk sensing pixel group. The cross-talk sensing pixel group includes a first green sensing pixel including a first green color filter and a first yellow color filter; a red sensing pixel including a second yellow color filter and a red color filter; a blue sensing pixel including a blue color filter and a first cyan color filter; and a second green sensing pixel including a second cyan color filter and a second green color filter.

Abstract: Semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. The second gate isolation structure may be formed on a shallow trench isolation feature. The height of the first gate isolation structure is less than the height of the second gate isolation structure. The composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. In some implementations, the first gate isolation structure is formed concurrently with gate spacers.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a stacked film including a plurality of first layers and a plurality of second layers alternately provided on the substrate. The device further includes a charge storage layer provided on a side face of the stacked film via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. Furthermore, one of the plurality of first layers includes a first region that includes carbon having a first concentration, and a second region that includes carbon having a second concentration higher than the first concentration, and includes a lower side region provided on a lower side of the first region or an upper side region provided on an upper side of the first region.

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

Abstract: Methods and systems for selectively forming phosphorus-doped epitaxial material. The methods can be used to selectively form the phosphorus-doped epitaxial material within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

Abstract: A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

Abstract: A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.

Abstract: The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.

Abstract: A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

Abstract: The present application provides a backside illuminated CMOS image sensor and a method of making the same. The backside illuminated CMOS image sensor comprises: a pixel region substrate, an isolation structure, a first dielectric layer, a metal grid, and second dielectric layer, wherein grid trenches and a metal plug are formed in the pixel region substrate, the isolation structure is located in each of the grid trenches and on the surface of the pixel region substrate outside of the grid trenches, and the isolation structure comprises a high-K dielectric layer, an insulating layer, and a metal core layer.

Abstract: According to the present disclosure, hybrid fins positioned between two different epitaxial source/drain features are recessed to prevent conductive material from entering interior air gaps of the hybrid fins, thus, preventing short circuit between source/drain contacts and gate electrodes. Recessing the hybrid fins may be achieved by enlarging mask during semiconductor fin etch back, therefore, without increasing production cost.

Abstract: A display device includes a substrate including a pixel area, and a pixel disposed in the pixel area and including an emission area and a non-emission area. The pixel includes a first alignment electrode and a second alignment electrode spaced from each other on the substrate, an insulating layer disposed on the first and second alignment electrodes, at least one light emitting element disposed on the insulating layer between the first alignment electrode and the second alignment electrode in the emission area, a pattern disposed between the at least one light emitting element and the insulating layer and including a hydrophilic group, and a bank disposed on the insulating layer in the non-emission area and including a first opening corresponding to the emission area and a second opening spaced from the first opening of the bank.

Abstract: A semiconductor storage device according to an embodiment includes a stacked body and a pillar. The pillar includes an insulating core, a channel layer, and a memory film. A plurality of gate electrode layers included in the stacked body includes a plurality of first gate electrode layers and one or more second gate electrode layers. The channel layer includes a first portion and a second portion. The first portion is provided between an uppermost first gate electrode layer and the insulating core. The second portion extends from a first height to a second height. A film thickness of the second portion is greater than a film thickness of the first portion.