Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.

Abstract: A correlator is disclosed and includes a data bus for receiving blocks of n bit parallel in phase (I) and n bit parallel quadrature (Q) signal data and n bit parallel I and Q reference data from respective I and Q signal channels and I and Q reference channels. The I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce an I component signal output and Q component signal output along each of the individual n parallel paths. An output bus receives I and Q component signal outputs from the n parallel paths one at a time at one bit input time periods such that there is one correlation product output for every I and Q parallel n bits. A cascade adder circuit comprises at least one adder connected to the output bus and receives the I and Q component signal outputs from the output bus and delayed I and Q component signal outputs from another correlator.

Abstract: A communication system (700) comprises a plurality of base sites (702-708) which include a first antenna (712) for transmitting a synchronous communication protocol such as a paging protocol and a second antenna (714) for transmitting a rotating phase signal. A communication device (250) takes the synchronous communication protocol and develops a reference signal (220) from the received protocol. The communication device (250) takes the reference signal (220) and the received rotating phase signal (214) and uses a phase detector (216) to produce a phase difference signal (232) which is substantially equal to the angle of the communication device (250) with respect to the particular base site (702-708) which transmitted the signals. In order to determine the location of the communication device at least two such phase difference signals (232), one phase difference signal from at least two different base sites is determined.