Abstract: A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.